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During the development of modern semiconductor processes, which has increasing complexity and an extremely high number of degrees of freedom, a large number of distinct test structures are required to test and ensure the yield and manufacturability. To increase the utilization of chip area, addressable methodology of test chip is developed. In this paper, we present a novel large-scale addressable...
Today's multi-media electronic era is driven by the increasing demand for small multifunctional devices able to support diverse services. Unfortunately, the high levels of transistor integration and performance required by such devices lead to an unprecedented increase of on-chip power that significantly limits the battery lifetime and even poses reliability concerns. Several techniques have been...
Nanoscale CMOS technologies, which were sensitive to electrostatic discharge (ESD), have been widely used to implement radio-frequency (RF) integrated circuits. Against ESD damages, ESD protection design must be included in RF circuits. A novel modified LC-tank ESD protection design was presented in this work. Such ESD protection circuit had been designed for 60-GHz RF applications and verified in...
The effect of deliberate circuit mismatches in an LC VCO is investigated and it is shown that such mismatches can significantly reduce the oscillation start-up time. An analysis is presented that shows that the presence of mismatches results in a common-mode disturbance simultaneous with the turn-on of the tail current. The use of this technique is applied to a low-power transmitter for an ultra-wideband...
A wideband low power CML frequency divider suitable for the Ku band has been designed and fabricated in a 90nm CMOS technology. Simulated phase noise and sensitivity curves are validated through on-wafer probe measurements. The maximum operating frequency is 24 GHz while dissipating 2.25 mW from a 1.5 V supply, resulting in a power-delay product of just 11.7 fJ. The divider measures 34 µm × 42 µm,...
In this paper, the tapered-VTH methodology to design energy-efficient buffers in deep nanometer CMOS technology is deeply analyzed. Its effectiveness is demonstrated under various working conditions (variable final load, activity factor, supply voltage and process corner). Simulations based on a 45-nm technology showed that the tapered-VTH approach can provide a 3X energy reduction, at the parity...
Networks made up of bio-inspired neuron oscillatory circuits with nanoscale memristors may achieve the large connectivity and highly parallel processing power of biological systems. Memristor also has potential to reproduce the behavior of a biological synapse. As in a living creature the weight of a synapse is adapted by ionic flow through it, so the conductance of a memristor is controlled by flux...
Biological networks involve both regular and random connections. Moreover they employ more than one type of cells. Being widely used in bio-inspired systems, Cellular Neural Networks are practical to implement large networks due to their regularly defined connections between unit processors. However, this perfect regularity of the structure does not always match with applications. Although it is widely...
A ring oscillator is designed and implemented on standard 130nm CMOS technology for wide range frequency tuning purpose in a spectrum monitor receiver used in cognitive radio applications. The three-stage differential ring oscillator is tuned by an array of MOS varactors, which is controlled by a novel staggered voltage offset system for improved tuning linearity. The proposed ring oscillator achieves...
Recently, much attention have been paid to the methods for circuit analysis using wavelet transform. In particular, we have proposed the method which can choose the resolution of the wavelet adaptively. This method can fully bring out the orthogonal and the multiresolution properties of the wavelet, and the efficiency of the calculation can be improved. In this paper, we precisely evaluate the accuracy...
The paper presents the direct application of the signal flow graphs (SFG) in calculation of higher order derivatives (sensitivities) of the linear network functions. It is based on the adjoint networks, represented by SFG. Thanks to the application of SFG we can calculate the exact value of any order derivative of the output variables without knowing their solutions in explicit form. Moreover the...
This paper presents a single supply analog lock-in amplifier for processing sensor noisy signals in low-voltage low-power embedded applications. The proposed system is based on a dual channel architecture to eliminate the phase dependence and enable its use for both resistive and capacitive sensors. In addition, looking for a compact solution, instead of a sinusoidal input a square wave input which...
A method of analogue emulation of the memristor with its prescribed charge (qM) - flux (ϕM) constitutive relation is presented. The memristor is emulated via a resistor with nonlinear current (iR) - voltage (vR) relationship, and a mutator. The purpose of the mutator is to provide a similarity transformation of the current-voltage characteristic of the resistor into the constitutive relation of the...
The paper introduces a novel sinusoidal quadrature oscillator (QO) with low harmonic distortion. The oscillator utilizes the non-linear non-inertial principle for amplitude stabilization and thus a fast transition to 0 steady state oscillations should be accomplished. This feature makes the QO suitable for operation at very low frequencies. The oscillator operates in the current-mode and is is intended...
In the statistical static timing analysis (S-STA), the timing information, such as a gate delay, a signal arrival time, and a slack, is treated as a random variable, and the statistical maximum operation is an important basic operation. Since the maximum of two Gaussian random variables is not Gaussian, various techniques for representing a non-Gaussian distribution have been proposed. Among them,...
One of the most important developments in the wireless industry within the last decade was the digitization of RF circuitry. This was in response to the incredible advancements of the mainstream CMOS technology in both processing speed and circuit density, as well as the relentless push to reduce total solution costs through integration of RF, analog and digital circuitry. Since the digital baseband...
This paper presents a novel architecture and its implementation for a versatile, miniaturised mote which can communicate concurrently using a variety of combinations of ISM bands, has increased processing capability, and interoperability with mainstream GSM technology. All these features are integrated in a small form factor platform. The platform can have many configurations which could satisfy a...
Scannerless 3D-Time-of-Flight image sensors serve to acquire three-dimensional (3D) information of objects in a scene. This contribution is devoted to modeling and calibration of scannerless 3D-Time-of-Flight image sensors based on pulse modulation. After a short description we introduce a 3D image sensor model that includes system nonlinearities due to nonideal photodetectors and signal processing...
This paper presents a design and measurements of multichannel integrated circuits in 90 nm CMOS dedicated to readout of hybrid pixels detectors in imaging applications. The chip contains a matrix of 40 × 32 pixels with the size of 100µm × 100µm. Each pixel contains a charge sensitive amplifier, a main amplifier stage, two discriminators with trim DACs and two 16-bit ripple counters. The nominal power...
This paper presents a design and measurements of multichannel integrated circuits dedicated to recording of neurobiological signals. 64 recording channels have been implemented in a single chip using a commercially available CMOS 180 nm process. A single recording amplifier consumes only 25 µW from 1.8 V supply and occupies 0.13 mm2 of the silicon area. Its main parameters such as the low/high cut...
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