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A new approach to an analog ultra-low power vision chip design is presented. The prototype chip performs low-level convolutional image processing algorithms in real time. The circuit is implemented in 0.35 µm CMOS technology, contains 64 × 64 SIMD matrix with embedded analogue processors APE (Analogue Processing Element). The photo-sensitive-matrix is of 2.2 µm × 2.2 µm size, giving the density of...
In this paper, we provide a novel approach to describe and analyze memristive circuits. This method is based on a Volterra series representation of the essential time functions of the circuit. This does not only provide the possibility of calculating voltages and currents over time in specific memristive networks, but describes the behavior of a general single memristor circuit, e.g. a circuit with...
In scale-space filtering signals are represented at several scales, each conveying different details of the original signal. Every new scale is the result of a smoothing operator on a former scale. In image processing, scale-space filtering is widely used in feature extractors as the Scale-Invariant Feature Transform (SIFT) algorithm. RC networks are posed as valid scale-space generators in focal-plane...
Incorporating multi-resolution capabilities into imagers renders additional power saving mechanisms in the subsequent image processing. In this paper, we show how, by exploiting a certain mask structure, 3 × 3 kernels can be reduced to 2 × 2 kernels if charge redistribution is provided at the focal plane of the imaging device. More precisely, by averaging and shifting a half-resolution pixel grid,...
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