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In this paper, a new CMOS exponential circuit with improved linear output range is presented. The proposed circuit is based on a new approximation function to increase the dB-linear output range. Simulation results in a 0.35 µm standard CMOS technology using HSPICE reveal an output range of 78 dB with errors less than ±1 dB. Also the Monte-Carlo simulation results for the threshold voltage variations...
An architecture for MDAC stages with low sensitivity to finite opamp gain is proposed, that allows designing high-precision pipeline ADCs in deep submicron technologies. The standard MDAC architecture is modified by inserting a voltage follower in the feedback path, and zero gain error is achieved if a relationship between the gain of the main opamp and of the opamp used in the voltage follower is...
In this paper we present a differential stage suitable to be used as the input stage of rail-to-rail very low-voltage opamps. The topology exploits an input level-shifter to keep the common-mode input voltage of a pseudo-differential pair constant, thus providing a constant gain over the whole input common-mode range. The main drawback of the proposed solution is the need of a switched-capacitor level-shifter,...
A low-noise transconductance amplifier (LNTA) aimed at continuous-time ΣΔ wideband frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65nm CMOS, achieves in simulation the noise figure less than 1.35 dB and linearity...
In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage...
This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity...
In this paper we present a low-power low-voltage class-AB amplifier with rail-to-rail output swing capable of operating from 0.5V to 1.0V of supply voltage, and two Sample & Hold (SHA) circuits based on this amplifier. The bias current and the bandwidth of the amplifier depend on the voltage supply, so that for low-power operation a low supply voltage can be used. The two SHAs have a nominal gain...
A 2.4-GHz CMOS single ended-input differential-output front-end built with a common source low noise amplifier (CS-LNA) and a switched transconductor mixer (SW-MIX) is presented. The circuit is designed and optimized to work in a ZigBee receiver. Since this is a low power consumption standard, a single-ended LNA is preferred over a fully-differential topology because it leads to lower cost in area...
This paper presents the design of a low noise amplifier in 180 nm CMOS based on a figure-of-merit optimization technique. The proposed figure-of-merit for the given amplifier topology combines the trade-off between accuracy and current consumption, which is a typical trade-off for most low noise amplifiers. In addition, the chosen figure-of-merit is shown to have similar form as the figure-of-merit...
This paper presents a new CMOS analog equalizer for short-reach optical communications. The circuit has been designed in a standard 0.18 µm CMOS process. The equalizer is aimed for multi-gigabit short-range applications, targeting up to 3.125 Gbps through a 50 m SI-POF. The proposed structure operates with a supply voltage of 1 V and has a power consumption of 2.5 mW.
This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ−Δ) Modulator to measure and assess its performance. The CT Σ−Δ modulator/decimation filter cascade...
This paper employs a CMOS 0.18 µm CMOS technology to design a 6-bit 250 MS/s pipelined ADC with open-loop amplifiers. The amplifiers utilize MOS transistors in triode region instead of resistors and current sources to decrease the process variation and the need of bias circuits. The amplification managed with the global-gain-control loop which realizes the error amplifier with a comparator in low-bandwidth...
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