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This paper considers the analysis and the design of an array of two NMOS differential oscillators coupled through a resistor. A new writing of the nonlinear equations proposed by R. York to describe the oscillators' locked states but limited for the specific case of a resistive coupling is presented. The new system permits the calculation of the free-running frequencies of the oscillators when a specific...
During the development of modern semiconductor processes, which has increasing complexity and an extremely high number of degrees of freedom, a large number of distinct test structures are required to test and ensure the yield and manufacturability. To increase the utilization of chip area, addressable methodology of test chip is developed. In this paper, we present a novel large-scale addressable...
This paper describes a low-power fully differential cyclic ADC. It utilizes a 3-bit C-2C ladder to achieve 9-bit resolution. For the 9-bit resolution the 3-bit C-2C ladder occupies 64 times less area than a binary weighted capacitance array. The operational amplifier with the slew rate detection is used in order to increase the speed of the ADC. The simulated power consumption of the ADC is 33 µW@3...
One of the missing critical on-board safety equipment of the Unmanned Arial Vehicles (UAVs) is the collision avoidance system. In 2010 we launched a project to research and develop an SAA system for UAS. As the system will be on-board in a small aircraft we have to minimize the weight, the volume, and the power consumption. The acceptable power consumption is 1–2W and the mass of the control system...
As one of adaptive lattice dynamics, a nonlinear dynamical model with threshold activated coupling has been proposed by S. Sinha since 1994. In this model, each lattice site performs an arbitrary nonlinear transformation and thresholding. The excess of an output over the threshold is transported to the neighboring lattice site(s). This dynamics generates various spatiotemporal patterns. S. Sinha,...
Incorporating multi-resolution capabilities into imagers renders additional power saving mechanisms in the subsequent image processing. In this paper, we show how, by exploiting a certain mask structure, 3 × 3 kernels can be reduced to 2 × 2 kernels if charge redistribution is provided at the focal plane of the imaging device. More precisely, by averaging and shifting a half-resolution pixel grid,...
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