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A digital wave filter operating on bandpass sigma-delta (SD) modulated signals is presented in this paper. The filter is obtained by a z-domain transformation of a baseband SD domain filter which is a binary-quantized discrete model of an analog distributed parameter filter (ADPF). Thus, the design properties of various ADPFs can be utilized for constructing the presented type of digital filters....
The optimization of fixed coefficient FIR filter implementation has been focused mainly on the multiplier block where full precision fixed point arithmetic is normally used. Recently, an optimization method was proposed for the structural adders in FIR filters. This paper further proposes a method for gradually reducing the number of fractional bits within the structural adder block such that the...
The paper presents a package of arithmetic operation synthesis dedicated to reconfigurable logic controllers programmed according to IEC1131 and EN61131. The program is compiled to hardware structure with a massive parallel processing. The developed method automatically allocates resources and operations. It controls resource usage and operation timing. Using mixed concept of operation allocation...
The Discrete wavelet transform (DWT) has been used in a wide range of real-time application. Algebraic integer quantization (AIQ) encoding has been proposed to represent the irrational transform basis of the wavelet transform as polynomials with integer coefficients. In this paper, we suggest to restate these polynomials to obtain simpler coefficients for both the integer coefficients and the polynomial...
This paper proposes a method to design low-delay fractional delay (FD) filters, using the Farrow structure. The proposed method employs both linear-phase and nonlinear-phase finite-length impulse response (FIR) subfilters. This is in contrast to conventional methods that utilize only nonlinear-phase FIR subfilters. Two design cases are considered. The first case uses nonlinear-phase FIR filters in...
Computing Euclidean Distances is a very important operation in digital communication, especially in the case of trellis coded modulation, where it is used numerously. This paper shows that a substantial reduction in complexity can be achieved in hardware processing elements for computing Euclidean Distances. A reduction in complexity down to 39% is shown compared to traditional designs. The paper...
This paper shows a novel methodology to reduce the power consumption and complexity in unrolled CORDIC architectures. It is a methodology based on removing adder and subtractor stages starting from the first stage. The stages are replaced with a number of MUXes. Three to four stages can be removed with substantial reduction in complexity and power consumption. The methodology is applicable on CORDICs...
In this paper, modified, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and power consumption. Two different architectures are investigated, both have variable configurations of the input and output word-length (i.e., the physical resolution of the DAC). A modified architecture, termed in this work...
Current methods used to design multiplierless digital filter have demonstrated their potential to construct low complexity circuits from multiplier blocks with few adders in order to replace the multipliers of standard Finite Impulse Response structures. However, the traditional approach only provides a local optimization as it need to rely to defined circuit architectures, such as the direct form...
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