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This paper presents the design and functional simulation of a new multi-level bang-bang phase detector for use in a clock and data recovery circuit (CDR). The designed phase detector provides information of the nature of the delay between its input signals in a digitised manner, establishing six levels of quantisation. To avoid the metastability that hinders the performance of traditional bang-bang...
This paper proposes a new Built-In Self Test architecture to detect time interval errors (TIE) of Phase-Locked Loops. A transient current sensor utilizing Flipped Voltage Follower (FVF) is used with a comparison block in the proposed topology. It is designed and verified for IBM 65nm technology using 1 V supply voltage and capable of detecting both steady-state and transient currents up to 150 µA...
Existing works on generating random bits by ring oscillators (ROs) mostly do not have detailed analysis on phase noise and jitter which are the entropy source of a random number generator. This paper analyzes the suitability of existing ROs for random number generation and possible improvements in order to increase the randomness of a RO. Randomness equations are derived, to understand efficiency...
A Continuous-Time Sigma-Delta (ΣΔ) Modulator for Bluetooth with 52MHz sampling frequency in a 1.2V 65nm CMOS process is presented. The modulator has a proposed single-stage 3rd-order 4-bit architecture, which employs a dual-loop feedback method to compensate the loop delay up to one clock period. A 4-bit flash ADC and a 4-bit current-steering DAC are used to improve the resolution and stability. Non-Return-Zero...
The effects of circuit non-idealities in a “Hogge ” -type phase detector are examined. Using a behavioral model for each circuit block, it is shown that various circuit non-idealities introduce static phase offset in the phase detector, reduce the monotonic range of its transfer characteristics and eventually degrade the capture range and jitter tolerance of the clock and data recovery (CDR) loop...
An analysis of frequency control techniques for inverter based ring oscillators is presented. The aim of this study is to aid the circuit designer in architecture selection appropriate for a specific application. A brief discussion on ring oscillators is presented followed by an overview of the various control schemes. The circuits are realized in a 40 nm CMOS technology and simulated using Spectre...
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