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This paper presents two integrated class-A travelling wave medium power amplifiers employing 0.35µm SiGe HBT process. The first amplifier realized is a 1.3×1mm2 device comprising of a single-stage configuration using a single transistor that exhibits an average small-signal gain of 7dB and power level of 14dBm between 0.25 to 2.5GHz while maintaining power-added efficiency in the range 30% to 10%...
A wideband low power CML frequency divider suitable for the Ku band has been designed and fabricated in a 90nm CMOS technology. Simulated phase noise and sensitivity curves are validated through on-wafer probe measurements. The maximum operating frequency is 24 GHz while dissipating 2.25 mW from a 1.5 V supply, resulting in a power-delay product of just 11.7 fJ. The divider measures 34 µm × 42 µm,...
This paper presents a single supply analog lock-in amplifier for processing sensor noisy signals in low-voltage low-power embedded applications. The proposed system is based on a dual channel architecture to eliminate the phase dependence and enable its use for both resistive and capacitive sensors. In addition, looking for a compact solution, instead of a sinusoidal input a square wave input which...
This paper presents a design and measurements of multichannel integrated circuits dedicated to recording of neurobiological signals. 64 recording channels have been implemented in a single chip using a commercially available CMOS 180 nm process. A single recording amplifier consumes only 25 µW from 1.8 V supply and occupies 0.13 mm2 of the silicon area. Its main parameters such as the low/high cut...
The effect of nonlinearities in injection-locked frequency dividers is investigated and it is shown that the presence of nonlinearities, such as in a CML DFF-based divider, results in a wider frequency locking range. A new divider topology is presented that exhibits both higher operating frequencies and similar wide-locking range compared to the conventional CML DFF-based topology. The chip was fabricated...
Application of the ΣΔ modulation technique to the on-chip spectral test for high-speed A/D converters is presented. The harmonic HD2/HD3 and intermodulation IM2/IM3 test is obtained with one-bit ΣΔ sequence stored in a cyclic memory or generated on line, and applied to an ADC under test through a driving buffer and a simple reconstruction filter. To achieve a dynamic range (DR) suitable for high-performance...
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