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In this paper, a new CMOS exponential circuit with improved linear output range is presented. The proposed circuit is based on a new approximation function to increase the dB-linear output range. Simulation results in a 0.35 µm standard CMOS technology using HSPICE reveal an output range of 78 dB with errors less than ±1 dB. Also the Monte-Carlo simulation results for the threshold voltage variations...
A wideband low power CML frequency divider suitable for the Ku band has been designed and fabricated in a 90nm CMOS technology. Simulated phase noise and sensitivity curves are validated through on-wafer probe measurements. The maximum operating frequency is 24 GHz while dissipating 2.25 mW from a 1.5 V supply, resulting in a power-delay product of just 11.7 fJ. The divider measures 34 µm × 42 µm,...
In this paper, the tapered-VTH methodology to design energy-efficient buffers in deep nanometer CMOS technology is deeply analyzed. Its effectiveness is demonstrated under various working conditions (variable final load, activity factor, supply voltage and process corner). Simulations based on a 45-nm technology showed that the tapered-VTH approach can provide a 3X energy reduction, at the parity...
One of the most important developments in the wireless industry within the last decade was the digitization of RF circuitry. This was in response to the incredible advancements of the mainstream CMOS technology in both processing speed and circuit density, as well as the relentless push to reduce total solution costs through integration of RF, analog and digital circuitry. Since the digital baseband...
This paper presents a design and measurements of multichannel integrated circuits dedicated to recording of neurobiological signals. 64 recording channels have been implemented in a single chip using a commercially available CMOS 180 nm process. A single recording amplifier consumes only 25 µW from 1.8 V supply and occupies 0.13 mm2 of the silicon area. Its main parameters such as the low/high cut...
An architecture for MDAC stages with low sensitivity to finite opamp gain is proposed, that allows designing high-precision pipeline ADCs in deep submicron technologies. The standard MDAC architecture is modified by inserting a voltage follower in the feedback path, and zero gain error is achieved if a relationship between the gain of the main opamp and of the opamp used in the voltage follower is...
Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-VT) systems. First, two sub-VT analysis methods are reviewed, both of which allow to evaluate the energy dissipation and performance in the sub-VT regime for designs which have been synthesized using a 65-nm CMOS SCL, characterized...
An empirical design optimization approach is explored for A/D-converter area efficiency. The die area consumption of commonly used ADC architectures is surveyed. Based on trends observed in a large set of empirical data, the area normalized to number of effective quantization steps is proposed as a generic measure of area efficiency. It is seen that state-of-the-art absolute area has a strong correlation...
This paper proposes an approach to realize a leapfrog filter with transmission zeros by using OTA-C integrators and resistor-based addition circuit instead of OTAs. This method has advantages of reduced number of active elements and spread of element values. A tenth-order bandpass filter is presented as a design example.
In this paper we present a differential stage suitable to be used as the input stage of rail-to-rail very low-voltage opamps. The topology exploits an input level-shifter to keep the common-mode input voltage of a pseudo-differential pair constant, thus providing a constant gain over the whole input common-mode range. The main drawback of the proposed solution is the need of a switched-capacitor level-shifter,...
In this paper, the impact of the NMOS/PMOS imbalance on Ultra-Low Voltage (ULV) circuits and their design is discussed within a unitary framework for the first time. Variations are shown to dramatically affect imbalance due to the long-tailed probability density and high variability. The impact of the imbalance on the minimum supply voltage VDD,min ensuring correct gate switching is studied analytically...
We propose a forced chaos generator with a CMOS variable active inductor circuit. Two values of the equivalent inductance of the active inductor in the proposed circuit are switched by an external periodic square-wave voltage, so that a stretching-and-folding mechanism of chaotic motion is realized. The chaotic dynamics are confirmed through SPICE simulations with TSMC 0.35 µm CMOS semiconductor process...
A recently built IC which implements a CMOS tunable classifier circuit is introduced and test results of an application are presented. The classifier circuit parameters are determined for Iris data set with an algorithm based on Fisher's linear discriminant analysis (LDA); the data is first soft then hard classified. The proposed circuit was fabricated using CMOS AMS 0.35 µm process parameters and...
Three representative class AB Current Mirror OTAs are analytically compared in term of the trade-off speed, current consumption and area. The approach presented allows to derive useful design guidelines. The analysis was validated by means of simulations considering a 90 nm CMOS technology.
A new approach to an analog ultra-low power vision chip design is presented. The prototype chip performs low-level convolutional image processing algorithms in real time. The circuit is implemented in 0.35 µm CMOS technology, contains 64 × 64 SIMD matrix with embedded analogue processors APE (Analogue Processing Element). The photo-sensitive-matrix is of 2.2 µm × 2.2 µm size, giving the density of...
In this paper, a new floating frequency dependent negative resistor (FDNR) simulator circuit is presented. The proposed circuits consist of two second generation negative current conveyors (CCII-) and two capacitor and one resistor. The presented topology enables the simulation of ideal floating FDNR. The performance of the proposed floating FDNR is demonstrated on a sixth order band pass filter....
A low-noise transconductance amplifier (LNTA) aimed at continuous-time ΣΔ wideband frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65nm CMOS, achieves in simulation the noise figure less than 1.35 dB and linearity...
This paper presents a novel approach to design a programmable-bandwidth amplifier intended for ultra-low-power switched-capacitor application. The proposed topology is based on the common load-compensated two-stage OTA. The GBW is enhanced by replicating the second amplifying stage. Implemented in a 65-nm CMOS technology and approved by the post-layout simulation, the GBW is programmed in three operation...
In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage...
The reduction of the oxide thickness in advanced CMOS processes is one of the many advantages of technology downscaling, as it favors the reduction of the threshold voltage shifts due to radiation-induced gate oxide trapped charge. This inherent radiation hardness of deep submicron processes can be further exploited using gate-enclosed layout transistors with an annular design. In this paper we present...
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