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In this paper, a new CMOS exponential circuit with improved linear output range is presented. The proposed circuit is based on a new approximation function to increase the dB-linear output range. Simulation results in a 0.35 µm standard CMOS technology using HSPICE reveal an output range of 78 dB with errors less than ±1 dB. Also the Monte-Carlo simulation results for the threshold voltage variations...
This paper presents two integrated class-A travelling wave medium power amplifiers employing 0.35µm SiGe HBT process. The first amplifier realized is a 1.3×1mm2 device comprising of a single-stage configuration using a single transistor that exhibits an average small-signal gain of 7dB and power level of 14dBm between 0.25 to 2.5GHz while maintaining power-added efficiency in the range 30% to 10%...
In this paper a novel Winner-Take-All (WTA) topology is presented which shows good trade-off between resolution and resolution speed, at the cost of some increase in power consumption. The proposed WTA is compared with other current-mode WTAs found in literature based on the same operation principle. All the topologies were designed in a 0.13µm CMOS process and characterized in terms of resolution,...
Computing Euclidean Distances is a very important operation in digital communication, especially in the case of trellis coded modulation, where it is used numerously. This paper shows that a substantial reduction in complexity can be achieved in hardware processing elements for computing Euclidean Distances. A reduction in complexity down to 39% is shown compared to traditional designs. The paper...
AM-PM distortion causes spectral regrowth in RF transmitters with modulated signals. One reason for AM-PM is the fact that signal-dependent transistor input capacitance pulls the frequency response of the input matching network and causes phase shift already at the input of the transistor. This paper studies the Miller capacitance effect in most common fixed-supply and supply modulated power amplifier...
In this paper we present a differential stage suitable to be used as the input stage of rail-to-rail very low-voltage opamps. The topology exploits an input level-shifter to keep the common-mode input voltage of a pseudo-differential pair constant, thus providing a constant gain over the whole input common-mode range. The main drawback of the proposed solution is the need of a switched-capacitor level-shifter,...
This paper shows a novel methodology to reduce the power consumption and complexity in unrolled CORDIC architectures. It is a methodology based on removing adder and subtractor stages starting from the first stage. The stages are replaced with a number of MUXes. Three to four stages can be removed with substantial reduction in complexity and power consumption. The methodology is applicable on CORDICs...
Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate the choice of technology, architecture, and implementation techniques that trade off performance for power savings. Energy-efficient design is often achieved for designs that are sensitive to technology and design parameters....
The reduction of the oxide thickness in advanced CMOS processes is one of the many advantages of technology downscaling, as it favors the reduction of the threshold voltage shifts due to radiation-induced gate oxide trapped charge. This inherent radiation hardness of deep submicron processes can be further exploited using gate-enclosed layout transistors with an annular design. In this paper we present...
The effect of nonlinearities in injection-locked frequency dividers is investigated and it is shown that the presence of nonlinearities, such as in a CML DFF-based divider, results in a wider frequency locking range. A new divider topology is presented that exhibits both higher operating frequencies and similar wide-locking range compared to the conventional CML DFF-based topology. The chip was fabricated...
A CMOS voltage-to-current converter is presented. It is based on a class AB current mirror with very low input resistance and a passive resistor connected to the input for voltage-to-current conversion. Class AB operation is achieved without extra supply voltage requirements or static power consumption, using Quasi-Floating Gate techniques. Measurement results of a differential configuration for a...
The problem of the correct evaluation of Q-factor appearing in Adler's equation for injection-locking is addressed. Investigation has shown that recent results presented in the literature, while extending applicability of the original method, do not completely account for nonlinear effects occurring when two-port active devices are involved. To overcome such limitation, use can be made of a newly...
Bioelectrical impedance measurements can be used in a wide range of clinical applications for monitoring and tissue characterization. Bioimpedance measurement applications need current drivers with high output impedance and stable current injection in the frequencies from DC to about 10 MHz. This paper presents an improved current driver based on a pair of balanced operational transconductance amplifiers...
This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity...
This paper presents a new architecture for a overcurrent detection system, dedicated to fully integrated class-D audio amplifiers, that uses half the comparators than conventional architectures. A detailed implementation for a 1-W bridge-tied load (BTL) class-D amplifier, on a 0.18 µm CMOS technology is presented, showing a reduction of 28.8% in current consumption and 23.5% in silicon area, when...
This paper presents analytical expressions for the sensitivity of a low power envelope detector driven by a weak RF signal in the presence of a blocking signal. The envelope detector has been proposed for low power Wake-Up radios in applications such as RFID and wireless sensor systems. The theoretical results are verified with simulations of a modern short channel MOS transistor in a commonly used...
Different ultra low voltage implementations of the minority-3 function are compared with respect to robustness, area and metrics including power, energy and delay. It is shown how entire synchronous or asynchronous systems could be made from minority-3 functions only, instead of traditional Boolean gates and memory. Chip measurements and simulations in 120, 90 and 65 nm technologies are used as background...
This paper presents the design of a low noise amplifier in 180 nm CMOS based on a figure-of-merit optimization technique. The proposed figure-of-merit for the given amplifier topology combines the trade-off between accuracy and current consumption, which is a typical trade-off for most low noise amplifiers. In addition, the chosen figure-of-merit is shown to have similar form as the figure-of-merit...
We present a low-voltage low-power CMOS tunable transconductor exploiting body gain boosting to increase the small-signal output resistance. As a distinctive feature, the proposed scheme allows the OTA transconductance to be tuned via the current biasing the gain-boosting circuit. The proposed transconductor has been designed in a 0.13-µm CMOS technology and powered from a 1.2-V supply. To show a...
This paper presents three compact and simple CMOS voltage-to-current (V-I) converter schemes attaining rail-to-rail operation with a highly linear V-I relationship over a (−40, +140 °C) temperature range. Based on an OTA/common source amplifier configuration, the key idea to reach rail-to-rail operation is reducing the voltage across the linear resistor that performs the V-I conversion to keep the...
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