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In this paper we present a differential stage suitable to be used as the input stage of rail-to-rail very low-voltage opamps. The topology exploits an input level-shifter to keep the common-mode input voltage of a pseudo-differential pair constant, thus providing a constant gain over the whole input common-mode range. The main drawback of the proposed solution is the need of a switched-capacitor level-shifter,...
This paper presents a novel approach to design a programmable-bandwidth amplifier intended for ultra-low-power switched-capacitor application. The proposed topology is based on the common load-compensated two-stage OTA. The GBW is enhanced by replicating the second amplifying stage. Implemented in a 65-nm CMOS technology and approved by the post-layout simulation, the GBW is programmed in three operation...
In this paper a novel CMOS latch is designed using a class-AB transconductor as a core. The static latch behavior is studied using a homotopy method which allows highlighting sufficient conditions for the transconductor to become a latch. These last conditions are general and can be used for the design of new latches and comparators. The proposed latch features high speed together with high power...
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