The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Today's multi-media electronic era is driven by the increasing demand for small multifunctional devices able to support diverse services. Unfortunately, the high levels of transistor integration and performance required by such devices lead to an unprecedented increase of on-chip power that significantly limits the battery lifetime and even poses reliability concerns. Several techniques have been...
A new cyclic ADC structure achieving capacitor mismatch insensitivity is presented. This technique enables cyclic ADC to obtain a very precise residue voltage in cycles independent of matching of capacitors. In addition, this new structure saves the die area of capacitors in the switched capacitor network by 25% and significantly reduces power consumption by up to 40%. A 12-bit 1.67MS/s cyclic ADC...
Galois field arithmetic circuits find wide variety of application in cryptography. Thus they faces majority of the hardware based attacks for malicious gain. Though there are many approaches that have been proposed to mitigate such malicious attacks, most of them are inappropriate for practical applicability due to various design drawbacks. It is noted that Galois field multipliers are one among the...
This paper proposes high performance dedicated hardware architecture for the Haar Wavelet transform, whose structure is based on nine levels of decomposition. The architecture is described in hardware description language VHDL, and it has been designed by using fixed point arithmetic, and also using efficient arithmetic operators into their sub modules. The efficiency of the architecture was proved...
This paper employs a CMOS 0.18 µm CMOS technology to design a 6-bit 250 MS/s pipelined ADC with open-loop amplifiers. The amplifiers utilize MOS transistors in triode region instead of resistors and current sources to decrease the process variation and the need of bias circuits. The amplification managed with the global-gain-control loop which realizes the error amplifier with a comparator in low-bandwidth...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.