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This paper presents a mobile security SoC to deal with intensive cryptography algorithms for different security protocols. A MIPS-like general processor, a dedicated package processor for fast data package, and multiple security processors for cryptography are integrated in the SoC. Moreover, the performance can be greatly enhanced by the well-designed DTU (Data Transfer Unit), memory architecture...
Because of the special p-i-n structure of the tunneling FET (TFET), many different composite transistors can be formed with careful device design by combining TFET with MOSFET. In this paper, we propose the special applications of TFET as memory devices. A novel capacitor-less DRAM cell based on floating junction gate (FJG) concept can be configured with TFET. In addition, several different memory...
Modular based partially and dynamically reconfigurable (PDR) FPGA system is an ideal solution for run-time image processing system which needs to change the function of the processing unit dynamically. Here we present a new PDR image filter based on our self-developed FDP FPGA Device. In this system, the transition bus (TB) structure is proposed for physical separation of the static/dynamic blocks...
SRAM sense amplifier plays a key role in memory design. With technology scaling to the nanometer, the device mismatch increases and the distribution effect induces unstable signal injection, thus affecting the reliability of memory system. This paper presents a new method for SRAM sense amplifier design. It incorporates reasonable delay between the passgate and enable signals to effectively mitigates...
A novel architecture of the configurable Distributed Random Access Memory (RAM) logic based on Look-Up Tables (LUTs) in the Logic Block (LB) is proposed and implemented in a tile-based FPGA manufactured with a 0.5μm SOI-CMOS logic process. The Distributed RAM can be configured in two modes: Single-Port RAM and Dual-Port RAM. Due to its resource abundance and low latency the Distributed RAM can complement...
This paper presents an optimized architecture of shared memory controller in packet processing multi-processor system on chip (MPSoC). The rotation priority algorithm in arbitration mechanism is ameliorated so that fairness of the memory access response and continuity of read/write commands are guaranteed. A `ping-pong' structure is adopted in SRAM interface logic which optimizes the memory data throughput...
In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (~ 84%) and the retention...
SCMOS is a low cost, high capacity, high speed, high yield, and power saving VLSI device platform technology for microelectronics chips and modules. Benefits include: (1) Uses the complementary Low threshold Schottky Barrier Diodes (LtSBD or simply SBD). (2) Integrated the SBD and CMOS transistor as basic circuit elements for Analog, Logic, and Memory (ALM) macros. (3) Single power supply chip. Circuits...
A radiation hardened 256K-bit asynchronous SRAM is presented. It is fabricated by a 0.5-micron, radiation hardened CMOS PDSOI process with 3 layers of metal. It features 800uA stand-by current, 42ns access time, 300K rad(Si) total dose tolerant and 1.5 × 1011rad (Si)/s dose rate survivability. A 28-pin DIP package is used. The circuit operates with ambient temperature from -55 to +125°C and power...
Field Programmable Gate Arrays (FPGAs) are used in a variety of applications. However, the SRAM-based FPGAs can be easily influenced by single event upset (SEU) in the configuration memory. SEU could lead to a series of catastrophic consequence ranging from unwanted functional, data loss, or failure of the whole systems. So it's very important to find a way to mitigating the SEU effect. In this paper,...
Low supply voltage is a commonly method for suppressing system power consumption and thermal effects, improving battery life and chip reliability for mobile SoC and 3D-IC devices. This paper describes various mainstream and emerging embedded non-volatile memory (eNVM) solutions for mobile SoC and 3D-IC designs. This study also reviews and discusses the key circuit technologies for decreasing the VDDmin...
As the MOSFET's channel length is scaling down, SRAM stability becomes the major concern for future technology. The cell becomes more susceptible to both process induced variation in device geometry and threshold voltage variability due to doping fluctuation in the channel region. In this paper, a novel highly stable 10T SRAM cell is proposed which eliminates read SNM during read and write operation...
The paper describes the parasitic structures of MOS transistors in SOI CMOS ICs at first. Then the influences of the parasitic structures on single particles radiation effect of MOS transistors in SOI CMOS ICs are presented. Finally the hardness methods of single event effects resulted by the parasitic structures of MOS transistors are given and the estimate about their excellence is made out.
In this paper, a novel low-power SRAM based on 4-transistor (4T) latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation...
High speed, low power and compatibility with standard technology Static random access memory (SRAM) is essential for system on chip (SoC) technology. In this paper, we first present a 6T-SRAM (1WR) and two types of 8T-SRAM cell(2WR 1W1R). After that how the (1W1R) cell work with external unit is explained, and we compare the SNM sensitivity and the write/read operations time of 1WR 1W1R cell.
This paper proposed a VLSI architecture of resisting long echo channel estimation which is based on the algorithm proposed in. FFT module reusing and clock gating are used in order to reduce the hardware complexity and power consumption. The synthesis results show that the area can be reduced to only 65.5% of architecture in which FFT modules are not be reused. And the power can also be reduced a...
So far the most aggressive manufacturing forecast for 22nm technology node is in late 2011, and there still remains many arguments for its next generation, 15nm manufacturing technologies. The major obstacles in front of the manufacturing are (1) high cost fine patterning technology, (2) tradeoff of SRAM cell size and performance, (3) increasing variability, (4) short channel effect control, etc....
The minimum operating voltage, Vmin, of memory-rich nanoscale CMOS LSIs is investigated to open the door to the below 0.5-V era. A new method using a timing margin is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the threshold-voltage variations, ΔVt, which become more significant with device scaling, and to the lowest necessary threshold voltage, Vt0, of MOSFETs. As a result...
According to architecture characteristics of the motor control digital signal processor (MCDSP), we select standard boundary scan test which is compatible with IEEE 1149.1 as main method, and full scan test as complementary method to test whole chip. Adopted self-definition address registers, data registers, control registers together, boundary scan test makes the use of the original core circuit...
For the past thirty years, the downscaling has been the guiding principle in the field of High-density semiconductor memories. However, recently, the limit of planar bulk MOSFETs is becoming apparent. Therefore, in order to extend the scalability of memory technology to the nano-scale generation, a new device structure is necessary. From the viewpoint, I will discuss future High density Memory with...
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