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The memory effect in floating nanodot gate field effect transistor (FET) was investigated by fabricating biomineralized inorganic nanodot embedded metal-oxide-semiconductor (MOS) devices. Artificially biomineralized Co oxide cores accommodated in ferritins were utilized as a charge storage node of floating gate memory. Two dimensional array of Co oxide core accommodated ferritin were, after selective...
This work presents a preliminary performance comparison between the new and conventional block oxide (BO) bulk-MOSFETs that suggests the proposed BO structure as a candidate for scaling planar CMOS to 16 nm generation and beyond. Also, the combined application of the isolation-last process (ILP) and the BO process provides a method of forming a new BO (NBO) structure that diminishes the short-channel...
The paper present an ultra-low power NEO using full-CMOS technology based on sub-threshold analog design. The ultra-low power NEO system includes a differentiator with a differential structure and a multiplier based on the dynamic translinear principle. The circuit has been designed in 0.35μm CMOS technology and with total current consumption of about 825 nA. As is demonstrated by the simulation results,...
Quantum-transport simulations of current-voltage characteristics are performed in nanoscale metal-oxide-semiconductor field-effect-transistors. Effects of interface roughness, discrete impurity, and phonon scattering are studied. Band-structure effects in p-type nanowire transistors are also investigated.
An improved mobility model for device simulation is presented. The model is based on charge density instead of effective surface electric field. Compared to the other models, it accounts for substrate bias effect and channel length dependence.
An improved negative level shifter with high speed and low power consumption is presented. To reduce the switching delay and power consumption, a boost circuit is designed and additional charging current paths are introduced in the improved level shifter. The circuit has been designed in 130nm triple-well standard CMOS technology with a nominal power supply VDD of 1.5V and a negative voltage of -4...
For NMOSFETs with tensile stress liner, the contact position and the neighboring gates affect the mechanical stress distribution in the device. The effects of symmetrical and asymmetrical layout on 22nm NMOSFETs are studied, and the performance of the device is compared.
This paper presents a cell balancing management for battery pack. It is used for each cell in battery pack to protect pack from damages such as overheating and overvoltage taken by the different performances between different cells, it manages individual cell with CC-CV charging strategy, shunts charge current smoothly to protect every cell preferably; in order to be suitable for different charge...
In this work, we study the impact of device self-heating on Bulk and double-gate silicon-on-insulator (DGSOI) technologies using self-consistent electrothermal (ET) simulations. Device characteristics of Bulk and DGSOI MOSFETs have been studied to estimate device performance and the impact of self-heating on the same. Self-heating effect (SHE) on the AC performance has also been studied for these...
Channel Hot Carrier (CHC) degradation on uniaxially strained pMOS and nMOS samples with different S/D materials has been analyzed. The results show that the CHC damage is larger in the strained samples in comparison with the unstrained devices, and increases with the temperature.
This paper discusses the design and implementation of a sample-and-hold circuit integrated into a high-speed and high-resolution A/D converter. In order to achieve the required speed and resolution, mixed MOS transistor channel length amplifier is used. The sample-and-hold circuit processes a differential 2.5-Vp-p output signal swing and achieves 16-bit linearity with sampling frequency up to 100...
The threshold voltage, Vth of a double-gate Schottky-Barrier (DGSB) source/drain (S/D) metal-oxide-semiconductor field-effect transistor (MOSFET) has been investigated. An analytic expression for surface potential in the channel is obtained and the results are verified via simulations, good agreement is observed. A new definition for Vth is given, and an analytic expression for Vth is presented. We...
In this paper, a short-channel subthreshold swing model for three-terminal (3T) double-gate (DG) MOSFETs with Gaussian doping profile in the vertical direction of the channel is presented. The effective conduction path effect concept of uniformly doped DG MOSFETs is utilized to incorporate the doping dependency in the present model. The effect of varying peak doping position of Gaussian profile on...
In this work, a low noise and low power charge sensitive preamplifier (CSA) based on CSMC 0.6 μm double poly mix CMOS technology was designed and simulated. In this design, two MOSFETs were used as a feedback resistor and a feedback capacitor respectively to replace an on-chip resistor in parallel and an on-chip capacitor in a conventional CSA. Simulation results show that this design can reduce the...
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to...
During the last few years, graphene has gained remarkable attention in the device community. Graphene transistors are evolving at a rapid pace and graphene-based devices are considered as an option for a post-Si electronics. To assess whether graphene can meet the high expectations or not, the properties and specifics of this new material have to be analyzed carefully. The present paper provides an...
In this paper, the C-V and I-V characteristics of Si-nanowire FET are presented. From the C-V data, the effects of undoped floating channel on the Si-nanowire FET are analyzed. Also, the intrinsic channel capacitance and mobility therein are extracted accurately by eliminating the effect of parasitic capacitances. Moreover, the I-V data free from the effect of the series resistance are obtained and...
Terahertz (THZ) detection by field effect transistors (FETs) has been paid great attention in recent years. This paper outlined the numerical study of terahertz radiation detection by FETs in our group, including the fundamental THz detection model, detection model with two sources, heterodyne detection model and optical beating model. These study results demonstrated the potential application of...
The paper describes the parasitic structures of MOS transistors in SOI CMOS ICs at first. Then the influences of the parasitic structures on single particles radiation effect of MOS transistors in SOI CMOS ICs are presented. Finally the hardness methods of single event effects resulted by the parasitic structures of MOS transistors are given and the estimate about their excellence is made out.
A new procedure to determine source/drain series resistance and effective channel length has been developed for MOSFETs operated in linear region. The gate-bias dependence of source/drain resistance is considered by differential and integration processes. This new-developed procedure has been applied to devices with mask channel lengths of 0.23, 0.2, and 0.185 μm. The parameters extracted with this...
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