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A methodology is presented for predicting the phase noise of the ΣΔ Fractional-N Frequency Synthesize that is both accurate and efficient based on sampling the noise voltage in the time domain. An accurate Voltage Control Oscillator (VCO) noise model is presented, including both thermal noise and 1/f noise. The behavioral model provides a great speed-up over the transistor level simulation and an...
A new extraction method for InGaP/GaAs HBTs based on direct optimization is proposed. Through modification of conventional GP formulation, the variations of transport saturation current and ideal forward transit time versus biases are incorporated into the compact model. Rather than intense and complicated iterative optimization, this new parameter extraction methodology realized the united optimization...
In this paper, we present an improved charge pump circuit for the non-volatile memories in RFID tags. The circuit consists of a single pumping branch without auxiliary capacitors and operates with a simple two-phase clock. The internal high voltages are used to control the gate and bulk terminals of the charge transfer switch. As a result, the threshold voltage loss and the leakage currents are eliminated...
An ion vertical striking on SOI CMOS transistor sensitive region creates an obvious large current resulting in upset of output node. Since parasitic BJT act, the single-event effect (SEE) is enhanced. In order to evaluate this effects, it is desirable to calculate critical charge (Qcrit, charge collected by the drain during the entire SEE) and the duration of output voltage pulse. With ISE TCAD, two-dimensional...
This paper gives a brief overview on recent advances in bipolar junction transistor (BJT) modeling and related simulation applications in circuit design. This work starts with a review of existing BJT compact model formulations, and covers a broad range of advanced topics such as precision temperature modeling, sub-circuit design, mismatch and corner modeling, and BJT scalable model.
A current buffer compensation Low Dropout (LDO) regulator for portable applications is present in this paper. The current buffer compensation scheme is a current feedback amplifier, which provides low output impendence in order to move the non-dominant pole due to the large gate capacitance of the pass transistor of the LDO regulator to high frequency. This LDO circuit had been designed and implemented...
With increasing scale of Network-on-Chips (NoCs), the power caused by long line wires between cores counts for a significant proportion of the NoCs energy consumption. Most of the study on NoCs topologies assume that interconnect wires between cores are same length and are short lines. Taking 2D 4×4 torus network as an example in this paper, we present a long line interconnects network model for analyzing...
A fast integrated gate driver with amorphous silicon thin film transistor (a-Si:H TFT) is proposed in this paper. To improve the circuit speed, a new input scheme is designed to provide a full scale pre-charge voltage. So the loss of pre-charge voltage, a challenge in the conventional designs, is avoided. Simulations show that the proposed gate driver has a much improved driving speed in comparison...
This paper presents a new poly-Si thin film transistor (TFT) pixel circuit for active-matrix organic light-emitting diode (AMOLED) displays. The pixel circuit has a simple four-transistor configuration and is controlled by two adjacent gate scan pulses, allowing a small circuit area and simple driving scheme. Simulation results show that this pixel circuit can provide the OLED with a current non-uniformity...
Stability is a critical design issue for radiation detection readout circuit when high counting rate together with low power property is simultaneously required. In this letter a novel method which increases the phase margin of the pulse shaper is presented. A readout circuit using this compensation technique has been implemented in 0.35 μ CMOS technology. Simulation and test results show that this...
The unbalanced speed for writing 0 (Reset) and 1 (Set) of phase change memory (PCM) causes lots of internal timing fragmentation during conventional parallel writing process. This fragmentation is the bottleneck of PCM writing speed. In this work, a novel self-write method is developed to eliminate fragmentation and enhance write throughout. The experimental result shows that this method enhances...
This paper presents a high gain and wide bandwidth fully differential operational amplifier (op amp) used in a sample and hold amplifier (SHA) circuit for a 12bit, 50Ms/s pipelined ADC. The gain-boosted technique is adopted to achieve a high gain without reduction of the output swing, while a new frequency compensation method is developed to compensate the bandwidth degradation caused by the gain-boosted...
In this paper, two high-resolution medium-bandwidth single-loop 4th-order single-bit sigma-delta modulators using a feed-forward and a feedback topology respectively are implemented in 0.13μm CMOS technology. The oversampling ratio is 50 with 312.5kHz input bandwidth, 14.66-bit and 16.62-bit resolution have been reached. The two circuits each consume about 8-mW from a single 1.2V supply voltage. After...
In this work, a low noise and low power charge sensitive preamplifier (CSA) based on CSMC 0.6 μm double poly mix CMOS technology was designed and simulated. In this design, two MOSFETs were used as a feedback resistor and a feedback capacitor respectively to replace an on-chip resistor in parallel and an on-chip capacitor in a conventional CSA. Simulation results show that this design can reduce the...
With the development of VLSI technology, logic circuits are becoming more and more vulnerable to soft errors due to particle hits. In order to guide reliable logic circuit design, it is important to develop efficient tools for soft error rate estimation. In this paper, we present a framework FAST for accurate SER estimation in logic circuits. FAST models detailed behaviors of transient pulses in logic...
In this paper, we use design planning method to partition a flat design based on SAED 90 nm process technology into blocks and created interface logic models (ILMs) for each blocks. Using the hierarchical design including ILM, the runtime of the place optimization stage, clock optimization stage and route optimization stage is reduced to 28.8%, 27.7% and 43% relatively, meanwhile the boundary timing...
Mechanisms during low pressure deposition (LPCVD) process in Micro-Electro-Mechanical Systems (MEMS) and Integrated Circuits (IC) fabrication have been analyzed. The LPCVD process has then been successfully simulated based on the re-emission models with Monte Carlo method and the Lagrangian method (shorthand denoted as L-type method) for boundary movement simulation. Simulation results show an agreement...
At the present IC technologies, the accurately extraction of the interconnects parasitic parameters become more important. But for the time consuming, that computing the parameters of interconnects with field solver directly is impracticable. The common way is that establishing the pattern library according some typical Structures at the early design stage, then calculating the actual parameters after...
An accurate wide-band compact model with proximity effects for on-chip transformers has been developed. According to the physical origin of the elements, method to determine parameters of these elements are offered. Furthermore, a new structure for transformers with high k (coupling coefficient) value has been proposed. Model verification with EM-simulation data of this structure demonstrates the...
This paper introduces an unified approach for modeling Switched-mode Power supplies (SMPS) in Matlab/Simulink, starting from a piecewise-linear (PWL) model, which is symbolically derived from schematic representation of circuit, and an hybrid automaton. The proposed framework includes efficient Simulink models for PWL systems, open and closed-loop sampled-data models, linear and non-linear average...
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