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A novel methodology to statistically analyze the statistics on small device performance is presented for the first time. To verify the accuracy of analysis and modeling, TCAD simulation is used to mimic possible process-induced and random fluctuations. The proposed approach precisely decouples various process dependency of the device electric behavior and predicts the device performance trend induced...
A 2D analytical model of the bulk-silicon triple RESURF devices is proposed. Based on the 2D Poisson's solution, the new analytical expressions of the surface potential and electric field distributions are obtained. According to the model and the semiconductor device simulator Medici, the electric field reduction mechanism and breakdown characteristics in the device are discussed. Further, a RESURF...
With increasing scale of Network-on-Chips (NoCs), the power caused by long line wires between cores counts for a significant proportion of the NoCs energy consumption. Most of the study on NoCs topologies assume that interconnect wires between cores are same length and are short lines. Taking 2D 4×4 torus network as an example in this paper, we present a long line interconnects network model for analyzing...
Variability from different sources such as layout-dependent effects due to strain has been a main obstacle against aggressive design rules and reducing corner margins in 32nm node and beyond. This paper reports and demonstrates a model development and verification platform to accurately address layout dependences due to strain. This platform has been successfully used in real design exercises at 40nm...
The threshold voltage, Vth of a double-gate Schottky-Barrier (DGSB) source/drain (S/D) metal-oxide-semiconductor field-effect transistor (MOSFET) has been investigated. An analytic expression for surface potential in the channel is obtained and the results are verified via simulations, good agreement is observed. A new definition for Vth is given, and an analytic expression for Vth is presented. We...
This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quasi-ballistic effects. The model incorporates the dependence of channel length, gate height and width, gate-to-contact spacing, nanowire size, multiple channels, as well as 1-D ultra-narrow...
The dual-material gate and asymmetrical halo structure is used in surrounding gate MOSFET to improve the performance. By treating the device as three surrounding-gate MOSFETs connecting in series and maintaining current continuity, a comprehensive drain current model is developed for it. It is concluded that the device also exhibits increased current drivability and improved hot carrier reliability...
An analytical model for high voltage Thin-film Silicon-On-Insulator (TSOI) lateral devices is proposed in this paper. A new Reduced SURface Field (RESURF) criterion is obtained for TSOI lateral devices with a lateral linear doping in the drift region. The optimum drift doping profile for TSOI lateral devices can be obtained from the new RESURF criterion. The analytical results are in good agreement...
This paper introduces an unified approach for modeling Switched-mode Power supplies (SMPS) in Matlab/Simulink, starting from a piecewise-linear (PWL) model, which is symbolically derived from schematic representation of circuit, and an hybrid automaton. The proposed framework includes efficient Simulink models for PWL systems, open and closed-loop sampled-data models, linear and non-linear average...
The edge field enhanced deep depletion phenomenon in metal-oxide-semiconductor (MOS) structure was demonstrated. The analysis in inversion to deep depletion of ultra-thin SiO2 and HfO2 was conducted using critical field model. By examine the field ratio between edge and bulk, it is observed that the HfO2 has larger ratio than SiO2. It is supposed the edge field enhanced deep depletion phenomenon dominates...
Based on the exact solution of the Poisson's equation, a new two-dimensional (2-D) model for the silicon-on-insulator (SOI) fully-depleted four-gate transistor(G4-FET) is successfully developed. The model is verified by its good agreement with the numerical simulation of the device simulator. For the threshold voltage degradation, it is found that the lateral coupling effects between lateral gate...
Negative bias temperature instability (NBTI) has become one of the major limiters for product lifetime, and various models have been proposed in order to explain NBTI. In this paper, an analytical model for DC NBTI and AC NBTI is proposed. This model describes the different time dependence of DC NBTI degradation at both short- and long-term stresses, and also reproduces the frequency and duty cycle...
The metal-oxide-semiconductor field-effect transistor (MOSFET) with a surrounding-gate (SG) is investigated. Poisson's Equation (PE) is solved analytically. The analytic expressions for electrical potential and threshold voltage (Vth) are obtained. The results are verified with Sentaurus simulations, good agreement is observed. The Vth model can be used for the integrated circuit designers.
In this paper, an advanced charge pump optimization methodology based on DOE technique is proposed. Compared with other optimization methods, this methodology constructs accurate mathematical models between the outputs and the input parameters with a few simulations through response surface technique and regression analysis. Moreover, owing to the simplification of the number of main charge pump input...
We have studied analytical model for performance variations of an extremely thin SOI-FET (ETSOI-FET) with an intrinsic Si (i-Si) channel in ballistic and quasi-ballistic regions, because ETSOIs are candidate for suppressing the performance variations as well as Coulomb scattering of carriers in the channel. It is newly found that drain current in ballistic ETSOIs still fluctuates even in an i-Si channel,...
One way to increase the breakdown voltage in heterojunction field-effect-transistors (HFETs) on silicon substrate is to introduce a transition (buffer) layer made of a sandwich of thin AlN/AlGaN layers between the silicon substrate and the GaN well. The effect of this transition layer is to average out and, in this way, to reduce the local mechanical stress that appears between the silicon substrate...
A cell-based analytical percolation model recently proposed for the dielectric breakdown (BD) of high-K stack gate dielectrics is reformulated in terms of competing local percolation paths. The model is equivalent to kinetic Monte Carlo implementation of percolation and it is shown to be consistent with large sample size statistical data. This is a physics-based picture that predicts the scaling of...
MOS device aging caused by hot-carrier injection (HCI) and negative/positive bias-temperature instability (N/PBTI) is increasingly more responsible for IC reliability failure for advanced process technology nodes. Accurate aging modeling and fast yet trustable reliability signoff are thus mandatory in process development and circuit design. This paper will first present an aging model that takes into...
Three-Dimensional (3D) integration will take the next stage VLSI technology instead of 2D technology. In 3D chip, the electrical performances are much better than in 2D chip, for its short length. In this paper, an accurate energy consumption model of 3D Through-Silicon-Via (TSV) is proposed for power estimation of 3D Network- on-Chip (NoC). The capacitance model of isolated TSV is analyzed in detail,...
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