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This paper provides a comprehensive guideline to design high efficient Si thin film solar cells via surface periodic Si nanopillars (SiNP) array texturing. A power conversion efficiency of ~18.1% is predicted to be achievable for the cell consisting of the SiNP array (array periodicity of 500 nm, SiNP diameter of 250 nm, and SiNP length of 1000 nm) on 800 nm thick underlying Si film based on the optical...
The internal gettering (IG) of Cu contamination in Czochralski (Cz) silicon wafers has been investigated using both a conventional IG process based on high-low-high (H-L-H) annealing and a rapid-thermal-process (RTP) based magic denuded zone (MDZ) process. It is found that a denuded zone (DZ) and bulk micro-defects (BMDs) acting as the gettering sites were formed in both cases. However, after cross-sectional...
The 5-nm-thick HfO2 film doped with 35 mol% Gd2O3 (GDH) as a high k dielectric has been epitaxially grown on Si (100) substrate by pulsed laser deposition (PLD). In situ reflection high-energy electron diffraction (RHEED) evolution of the (100)-oriented GDH during the deposition has been investigated and shows that a two-dimensional (2D) single crystalline GDH grows with a smooth surface. The in-plane...
The surface passivation properties of hydrogenated amorphous silicon suboxides (a-SiOx:H) deposited by plasma-enhanced chemical vapour deposition (PECVD) have been investigated. The process gases were nitrous oxide and a mixture of silane and helium at a deposition temperature of ~250 °C. Minority carrier lifetimes up to 270 us on 4·Ω·cm p-type float-zone silicon wafers were obtained. With thermal...
Reflectance spectrum calculations for a MgF2/diamond-like carbon(DLC)/DLC(or porous silicon (PS) ) silicon triple layer antireflection coating(ARCs) and the nanoporous silicon dioxide (NPSiO2) / DLC/DLC(or PS) triple layer ARCs are performed using the matrix method. The results are compared with the corresponding spectrum of a silicon oxynitride (SiOxNy)/PS, DLC/PS double layer ARCs and some triple...
We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<;10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting <;100> NW channel instead of <;110> NW, Ion = 1 mA/μm for Ioff = 100 nA/μm is achieved...
A fast integrated gate driver with amorphous silicon thin film transistor (a-Si:H TFT) is proposed in this paper. To improve the circuit speed, a new input scheme is designed to provide a full scale pre-charge voltage. So the loss of pre-charge voltage, a challenge in the conventional designs, is avoided. Simulations show that the proposed gate driver has a much improved driving speed in comparison...
This paper presents a new poly-Si thin film transistor (TFT) pixel circuit for active-matrix organic light-emitting diode (AMOLED) displays. The pixel circuit has a simple four-transistor configuration and is controlled by two adjacent gate scan pulses, allowing a small circuit area and simple driving scheme. Simulation results show that this pixel circuit can provide the OLED with a current non-uniformity...
Capacitance-voltage (C-V) and frequency dependent conductance-voltage (G-V) measurements have been carried out to investigate the charging and discharging effect induced by interface states and nanocrystalline Si (nc-Si) in floating gate MOS structures. Distinct conductance peaks are observed in the G-V curves for the floating gate with and without nc-Si dots. Based on the calculation of interface...
The activation characteristics of Si ion-implanted gallium nitride (GaN) have been investigated. High-resolution X-ray diffraction (HRXRD) analyses indicate that ion-implanted damage can be effectively recovered by rapid thermal annealing (RTA) up to 1100°C. With the implantation dose 1016cm-2, the sample presents strong n-type conductivity, reaching a maximum sheet carrier concentration 2×1015cm-2...
A new type of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with self-aligned metal electrodes (SAME) is systematically characterized. New device features different from conventional poly-Si TFTs are found, and are attributed to the presence of Schottky barriers at the channel ends.
Loss mechanism in the low-resistivity substrate degrades the quality factor of spiral inductors. This paper presents an efficient method to improve Q factor of spiral inductors based on standard low-resistivity silicon substrate by using patterned trench isolation. Both the inductors with and without patterned trench isolation have been designed and simulated by the three-dimensional electromagnetic...
Electron and hole mobility in sub-10nm silicon nanowire FETs on (100) SOI has been systematically investigated experimentally. The nanowire height of fabricated nanowire FETs is as low as 4 - 10nm and the minimum nanowire width is shrunk to 5nm. Higher hole mobility than (100) universal mobility is experimentally observed for the first time in 9nm-wide nanowire and even in 5nm-wide nanowire, while...
PIN tunneling field effect transistor (TFET) is one of the most promising devices due to its low sub-threshold swing. In this paper, using TCAD simulation, we investigate the doping and structure dependence of the electric field in PIN TFET. We show that an insertion of a thin N layer into PIN structure (i.e., PNIN TFET) not only enhances the drive current but also improves the reliability of the...
GaN is very promising for power switching transistors taking advantages of the high breakdown strength with high saturation electron velocity. The lateral and compact device configuration enables high speed switching with reduced on-state resistance and parasitic capacitance. In this paper, state-of-the-art device technologies of GaN transistor and its monolithic integration for switching applications...
A flexible, highly-sensitive, and easily fabricated carbon nanotubes (CNTs) tactile sensor is reported in this paper. CNTs are grown and patterned on bulk-micromachined silicon substrate with 3-dimensional surface profile. After polymer molding, the CNTs with 3-dimensional distribution are successfully transferred onto a flexible PDMS with 3-dimensional tactile-bump. Advantages of presented tactile...
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to...
Cubic silicon carbide (3C-SiC) has received a great deal of attention since it is a suitable material for electronic and MEMS devices operating in harsh environments. But difficulties still exist in realizing high throughput of high quality material. In the present paper, 3C-SiC layers have been grown on Si(111) in a vertical multi-wafer WCVD (Warm-wall Chemical Vapor Deposition) reactor with a rotating...
A new method for extraction of series resistance is proposed for poly-Si thin-film transistors. In this method, the extraction procedure is insensitive to the variation in effective channel length and device mobility, since both quantities are included in a single extracted parameter. The method has been successfully applied to a group of poly-Si TFTs with mask channel length from 2 to 30μm. Compared...
Summary form only given: CMOS at the 45 nm node has been in production for a couple of years now, and 32 nm CMOS is making its way into leading-edge products. If everything goes according to plan, CMOS at the 11 nm node should be in production in less than ten years from now. However, every technology has its limits and CMOS is no exception. While there will be billions of CMOS devices on a chip,...
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