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An analog baseband circuitry for a China Mobile Multimedia Broadcasting (CMMB) direct conversion tuner IC is introduced in this paper. It includes an 8th order channel select filter with sharp transition band and utilizes a novel gain-bandwidth-product (GBW) extension technique in designing the low power, high speed operational amplifiers (Op-Amps) of the active-RC filter. A current steering type...
To adapt to the rapid development of multi-standard mobile communication, a low noise amplifier (LNA) that can operate at two frequencies of 800MHz and 1.8GHz respectively was designed. SiGe HBTs with good noise performance were used in the design. The Cascode circuit topology was adopted to reduce the Miller effect of the transistor. Inductor degeneration in emitter was introduced to decouple the...
P-MOSFETs with HfO2 gate dielectric and TiN metal gate were fabricated on compressively strained SiGe layers with a Ge content of 50 at.% and electrically characterized. The devices showed good output and transfer characteristics. The hole mobility, extracted by a split C-V technique, presents a value of ~200 cm2/V·s in the strong inversion regime.
Ultrathin (11 nm) strained SiGe-on-insulator (SGOI) with a Ge fraction of 0.5 was fabricated by Ge condensation technique. The residual compressive strain as high as 1.72% was achieved in SGOI layer by reducing the initial thickness of as-grown Si0.93Ge0.07 layer. Strained-SGOI pMOSFET exhibits a hole mobility of 3 times higher than that of Si-on-insulator pMOSFET.
The concept of atomically controlled processing for group IV semiconductors is shown based on atomicorder surface reaction control in Si-based CVD epitaxial growth. Si epitaxial growth on B or P atomic layer formed on Si(100) or Si1-xGex (100) surfaces, is achieved at temperatures below 500°C. B doping dose of about 7× 1014 cm-2 is confined within an about 1 nm thick region, but the sheet carrier...
In this work, two kinds of thermal annealing methods were used to process the silicon wafer by Ge ion bombardment in two steps, dose of 7×1016/cm2 with 150KeV and dose of 2.72×1016/cm2 with 50KeV respectively. In order to control the defects density and Ge distribution in SiGe layer, furnace annealing (FA) and rapid thermal annealing (RTA) schedules were used. It has been found that the FA after ion...
Silicon-germanium dots grown in the Stranski-Krastanow mode are investigated as sources of strain for electron mobility enhancement in the silicon capping layer. N-channel MOSFETs with the channel in the Si cap-layer over the SiGe dot (DotFETs) are fabricated in a custom-made process and have an average increase in drain current of up to 22.5% compared to the reference devices. The sources of device...
Conventional solutions for dual-direction ESD protection have drawbacks in layout area (stacked unidirectional ESD clamps) and in process technology scaling (SCR-based solutions). To provide scalable protection, a new device architecture, based on a novel merged-collector dual-direction BJT-based ESD clamp, is proposed and successfully implemented in a 0.13 μm BiCMOS process.
Defects in SiGe-On-Insulator (SGOI) fabricated using Ge condensation by dry oxidation method were characterized by optical and electrical methods. The locations of main defect levels were determined to be above mid-gap for SGOI with low Ge fraction (Ge%), which tend to valance band direction and unintentionally induce high hole concentration in SGOI with increasing Ge%. The suppression of defects...
We present a novel bulk-Si dual-channel source/drain-tied (DCSDT) MOSFET with the multiple epitaxial growth of SiGe/Si layers, and selective SiGe removal to form the block oxide island (BOI). Based on the simulations, the SDT scheme achieves better DC characteristics than body-tied (BT) scheme such as: Ion (20% increased), Ioff (71% reduced), Rsd (5.3% decreased), S.S. (19% improved), DIBL (35% reduced),...
We have developed a new thermal CVD technique for poly-SiGe thin films that meets the requirements for low-cost fabrication of post-amorphous silicon (a-Si:H) TFTs, i.e., Reactive Thermal CVD featuring a set of reactive source materials of disilane (Si2H6) and germanium tetrafluoride (GeF4). We succeeded in deposition of poly-SiGe thin films at 450°C or higher on glass substrates by this technique...
Single-crystal Ge films on insulating substrates are desired to achieve advanced 3-dimensional large-scale integrated circuits (3D-LSIs) and thin-film transistors (TFTs). We have developed the rapid-melting Ge growth seeded from Si substrates, which achieves giant Ge on insulator (GOI) structures with (100), (110), and (111) orientations. Driving force to initiate the lateral growth is clarified as...
A novel multi-finger power SiGe heterojunction bipolar transistor (HBT) with non-uniform finger length and non-uniform finger spacing was proposed to improve the thermal stability. Thermal simulation for a ten-finger power SiGe HBT with novel structure was conducted with ANSYS software. Three-dimensional temperature distribution on emitter fingers was obtained. Compared with traditional structure...
Two approaches are proposed in this work to improve the operation characteristics of charge-trapping (CT) flash devices, namely, SiGe buried channel and stacked charge-trapping layer. SiGe buried channel with different Ge contents and various thicknesses of Si-cap layer on operation characteristics of CT flash devices were studied. The programming and erasing speeds of CT flash devices are significantly...
In this paper, we describe the performance elements used in our 28nm bulk devices with the gate first high-k/metal gate scheme for high performance applications. By using the innovative stressor integrations including improved stress memory technique (SMT), optimized embedded SiGe process and dual stress liner, Ieff of ~540/360 uA/um have been obtained for NMOS and PMOS respectively with the gate...
Integration of lanthanum lutetium oxide (LaLuO3) with a κ value of 30 is demonstrated on high mobility biaxially tensile strained Si (sSi) and compressively strained SiGe for fully depleted n/p-MOSFETs as a gate dielectric. N-MOSFETs on sSi fabricated with a full replacement gate process indicated very good electrical performance with steep subthreshold slopes of ~72 mV/dec and Ion/Ioff ratios up...
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