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The impact of a 60 MeV proton irradiation on the drain induced barrier lowering is investigated for tri-gate FinFETs processed with and without the implementation of different biaxial or uniaxial strain engineering techniques. A contrasting behavior is observed for n- and pFinFETs, which may be associated with the radiation-induced charges in the buried oxide and the influence of the back channel...
A structure with an asymmetric interfacial oxide layer is proposed to improve device performance in n-channel MOSFETs. The performance loss from mobility degradation, which results from thin interfacial oxide layers, can be mitigated by using a relatively thick interfacial oxide layer near source regions, while maintaining reasonable short channel effects through a relatively thin interfacial oxide...
We report a bias dependent body resistance model for deep submicron PDSOI technology. This model is well verified by the measured data based on the 0.35μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), and can be implemented in the SOI MOSFET compact model like BISMSOI.
Because of the special p-i-n structure of the tunneling FET (TFET), many different composite transistors can be formed with careful device design by combining TFET with MOSFET. In this paper, we propose the special applications of TFET as memory devices. A novel capacitor-less DRAM cell based on floating junction gate (FJG) concept can be configured with TFET. In addition, several different memory...
The memory effect in floating nanodot gate field effect transistor (FET) was investigated by fabricating biomineralized inorganic nanodot embedded metal-oxide-semiconductor (MOS) devices. Artificially biomineralized Co oxide cores accommodated in ferritins were utilized as a charge storage node of floating gate memory. Two dimensional array of Co oxide core accommodated ferritin were, after selective...
Nanotube electronics still faces significant challenges such as integration/assembly, co-existence of metallic and semiconducting nanotubes, and air-stable n-type nanotube transistor for complementary circuit operation. Here we report our solutions to these major obstacles, which may eventually lead to realistic and scalable nanotube integrated circuits. We report the wafer-scale synthesis, transfer...
In this study, we propose a new technology to fabricate pseudo tri-gate vertical (PTGV) MOSFETs without p-n junctions, named junctionless PTGVMOS (JPTGV). According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ~ 60mV/dec, Ion/Ioff ~ 1010, and low interface trap density are all achieved. The device without p-n junctions provides an easier way for...
This work presents a preliminary performance comparison between the new and conventional block oxide (BO) bulk-MOSFETs that suggests the proposed BO structure as a candidate for scaling planar CMOS to 16 nm generation and beyond. Also, the combined application of the isolation-last process (ILP) and the BO process provides a method of forming a new BO (NBO) structure that diminishes the short-channel...
In early days, our project team has analyzed the electric field, threshold voltage, capacitance, cut-off frequency and other characteristics of the double doping polysilicon gate MOSFET (DDPG-MOS), see references. In this study, the process steps of DDPG-MOS are designed and simulated with software TSUPREM. Then the frequency and transient characteristic of the device are analyzed using software MEDICI...
Two numerical simulation techniques are presented to investigate the heating issues in nanoscale Si devices. The first one is the Monte Carlo simulation for both electron and phonon transport, and the transient electrothermal analysis is carrier out in n+-n-n+ device with the n-layer length of 10 nm. The second is the molecular dynamics approach for simulating the atomic thermal vibration in the nanoscale...
An overview of metallic source/drain (MSD) contacts in nanoscaled MOSFET technology is provided in this paper. MSD contacts offer several benefits for nanoscaled CMOS, i.e., extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. In order to achieve high performance MSD MOSFETs, many design parameters such as Schottky barrier...
The review addresses the major challenges that Nanoelectronics will have to face in the next decades. A multifaced strategy is followed to scale down CMOS based technology with new materials and disruptive architectures, heterogeneous integration, alternatives to MOSFET for information processing introducing 3D schemes at the Front End and back end levels.
Analog circuit designs are often biased to work in sub-threshold mode with good gate-source voltage matching performances. Depending on the process, hump effect may change the MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. To model the hump effect, two narrow parasitic MOS are introduced in parallel with the main device. To accurately simulate matching...
The conventional threshold voltage shift measured by extrapolating transfer characteristics, ΔVth(ex), underestimates the NBTI-induced degradation of drain current, ΔId. Mobility degradation, Δμ, has been proposed as a potential contributor to ΔId. Evaluating Δμ, however, can be problematic and controversial. For test engineers, it is desirable to include all degradations in one parameter and we propose...
The transient effect of graded channel partially-depleted silicon-on-insulator nMOSFETs are analyzed by SILVACO ATLAS software. The switch on and switch off transient behaviors are studied for the device. While the device operates in the kink region, the transient effects of drain current were also investigated. It was found that the transient characteristic of the graded channel device was superior...
Several power and area efficient multi-bit quantizers are discussed in this paper. Through the comparison and analysis of the reported quantizers, a novel ultra-low power MOSFET-only micromation one for implantable neural applications is proposed to optimize the area and power consumption with the use of high density MOSCAP and dynamic comparators. Simulated in a 0.18 μm 1P6M CMOS process, the density...
Quantum-transport simulations of current-voltage characteristics are performed in nanoscale metal-oxide-semiconductor field-effect-transistors. Effects of interface roughness, discrete impurity, and phonon scattering are studied. Band-structure effects in p-type nanowire transistors are also investigated.
An improved mobility model for device simulation is presented. The model is based on charge density instead of effective surface electric field. Compared to the other models, it accounts for substrate bias effect and channel length dependence.
For NMOSFETs with tensile stress liner, the contact position and the neighboring gates affect the mechanical stress distribution in the device. The effects of symmetrical and asymmetrical layout on 22nm NMOSFETs are studied, and the performance of the device is compared.
A new planar-type body-connected FinFET structure produced by the isolation-last self-align process is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. The new process step first defines the gate region and then the active region, thus it can achieve fully self-alignment undoubtedly. Besides, due to the isolation-last process (ILP), an additional body region (ABR)...
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