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A single-loop second-order 3 bits ΔΣ modulator in 180 nm standard CMOS is presented. The design is intended to achieve high linearity in low-voltage low-power environment. The modulator achieves 89-dB SNDR and 98-dB SFDR in 20Hz~16kHz signal bandwidth, while the power consumption is 210 μW under 1-V supply voltage.
The paper present an ultra-low power NEO using full-CMOS technology based on sub-threshold analog design. The ultra-low power NEO system includes a differentiator with a differential structure and a multiplier based on the dynamic translinear principle. The circuit has been designed in 0.35μm CMOS technology and with total current consumption of about 825 nA. As is demonstrated by the simulation results,...
Analog circuit designs are often biased to work in sub-threshold mode with good gate-source voltage matching performances. Depending on the process, hump effect may change the MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. To model the hump effect, two narrow parasitic MOS are introduced in parallel with the main device. To accurately simulate matching...
A packaged VCO, which utilizes the heat-sink pad in Quad Flat Pack No-Lead (QFN) package to provide a ground connection for bonding wire inductors, is presented in this paper. The proposed VCO is designed to cover 4 to 5 GHz band and is able to work under a minimum of 0.9 V DC supply voltage with only 1 mW power consumption. It is fabricated in 0.18 μm standard CMOS process. It achieves the FOM of...
This paper presents a 8448MHz phase-locked loop (PLL) with a proposed divider implemented in 0.13 μm CMOS technology. Compared with conventional current mode logic (CML) divider, the proposed split-load divider presents wider operating frequency range and lower power dissipation. The ratio of the locking range over the center frequency is up to 70% depending on the operating frequency. It consumes...
In this paper, two novel structures at 200mV 0.18um sub-threshold full adders are proposed for wireless sensor network nodes or medical electronics. They use three state gate to enhance the transition time and drivability of carry out signal. Simulation results show that the transition time of the proposed structure using three state gate is 60% of that of old structure using transmission gate. The...
Several power and area efficient multi-bit quantizers are discussed in this paper. Through the comparison and analysis of the reported quantizers, a novel ultra-low power MOSFET-only micromation one for implantable neural applications is proposed to optimize the area and power consumption with the use of high density MOSCAP and dynamic comparators. Simulated in a 0.18 μm 1P6M CMOS process, the density...
An improved negative level shifter with high speed and low power consumption is presented. To reduce the switching delay and power consumption, a boost circuit is designed and additional charging current paths are introduced in the improved level shifter. The circuit has been designed in 130nm triple-well standard CMOS technology with a nominal power supply VDD of 1.5V and a negative voltage of -4...
In this paper a current mode logic (CML) transceiver with ±250mV output swing is proposed. The CML transceiver is designed according to inter-die communication model analysis. The model includes both bonding wire and transmission line based on electromagnetic analysis. The CML transceiver is implemented in 1.8V 0.18μm technology. Simulation results show that the transceiver can reach 2.4Gbps data...
A 0.13μm CMOS Direct-Conversion WiMAX/LTE transmitter with novel binary modulation gain control scheme and wide frequency band coverage is presented. In this work, binary modulation gain control realizes 36dB gain control at baseband frequency instead of by RF VGA at RF frequency. Output power is +0.5dBm and calculated EVM is 1.8%. A 4th order Butterworth low pass filter supports 2MHz~12MHz, 7-step...
Low supply voltage is a commonly method for suppressing system power consumption and thermal effects, improving battery life and chip reliability for mobile SoC and 3D-IC devices. This paper describes various mainstream and emerging embedded non-volatile memory (eNVM) solutions for mobile SoC and 3D-IC designs. This study also reviews and discusses the key circuit technologies for decreasing the VDDmin...
High and random voltages are big challenges for practical applications of organic thin film transistors (OTFTs). Herein, a route to achieve devices with both low operating voltages (Vop) and tunable threshold voltages (VTH) was proposed. The Vop was reduced to be less 3 V without lowering the mobility and the ratio of on/off current using a 30 nm Al2O3 insulator film fabricated by atomic layer deposition...
A switchable dual-band low power low noise amplifier operated at 900MHz/1.95GHz has been designed for GSM/TD-SCDMA applications using 0.13 μm CMOS process. To achieve noise matching and input matching at both bands, a tunable capacitance bank and a switchable inductor for L-match are utilized. Four gain modes are accommodated with current splitting technique at the second stage. The post-layout simulated...
Although audio-band sigma delta ADC has largely been implemented as discrete time circuits, a continuous time approach offers significant advantages for high accuracy low-power applications. A continuous time design allows for relaxed amplifier unity-gain bandwidth and power requirements. It also provides better noise immunity due to their inherent anti-aliasing properties. This paper introduces a...
This paper presents the design of 0.1-3.6GHz quad phase-locked loop (PLL) for multiple SerDes standards. The PLL has an adaptive bandwidth for different applications. But the bandwidth doesn't vary with processes and temperatures in every application condition for the process-dependent charge pump current and high precision bandap reference circuit. The core power of the PLL is 6.9mA at 3.125GHz without...
ADC is one of the key components employed in the digital controlled DC-DC converters. In this paper, a low power and high resolution algorithmic ADC is designed, which is suitable to the integrated digital controllers for high-frequency and low-power switched DC-DC converter. The designed 8-bit algorithmic ADC has 2 bits per stage. Simulation results show that ENOB up to 7.6bit is obtained. As one...
In this work, a low noise and low power charge sensitive preamplifier (CSA) based on CSMC 0.6 μm double poly mix CMOS technology was designed and simulated. In this design, two MOSFETs were used as a feedback resistor and a feedback capacitor respectively to replace an on-chip resistor in parallel and an on-chip capacitor in a conventional CSA. Simulation results show that this design can reduce the...
A successive approximation register analog-to-digital converter(SAR ADC) targeted for use in RSSI(received signal strength indicator) is presented. The measured signal-to-noise-and-distortion ratios(SNDR) of the ADC is 53.95 dB at 1MS/s sampling rate with power consumption of 147.6 μW from 1.2-V supply voltage, thus the resulting FOM is 0.437 pJ/conversion-step. The ADC is fabricated in a 0.13-μm...
In this paper, a novel low-power SRAM based on 4-transistor (4T) latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation...
In this paper, we designed a 1.2-V low supply voltage transconductance-C (Gm-C) low pass filter (LPF) for transmitter analog baseband front-end of wireless local area network (WLAN) transceiver applications. The filter's cut-off frequency is 10MHz and PIIP3 is 8.4dBm. The LPF uses a 3rd-order Chebyshev prototype. The filter is fabricated in TSMC 0.13-μm CMOS technology and drains 3.8mA from a 1.2-V...
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