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Drift diffusion models have been used extensively by the semiconductor device research community to provide a physics-based approach for the modeling and simulation of electronic devices under various bias conditions. In this article we develop a model based on the drift-diffusion equations for the simulation of Li-air batteries with organic electrolyte. The model is carefully calibrated and takes...
The paper present an ultra-low power NEO using full-CMOS technology based on sub-threshold analog design. The ultra-low power NEO system includes a differentiator with a differential structure and a multiplier based on the dynamic translinear principle. The circuit has been designed in 0.35μm CMOS technology and with total current consumption of about 825 nA. As is demonstrated by the simulation results,...
A wide tuning range LC VCO with auto amplitude control is designed in 0.13-μm CMOS. Phase noise optimized design for the wide tuning range VCO is discussed and a PVT insensitive digitally reconfigurable auto amplitude calibration (AAC) circuit is used to stabilize the phase noise in the whole wide band. The proposed AAC circuit with a code estimated FSM provides faster operation to get the optimum...
This paper presents a novel first-order temperature compensated current reference. The measured temperature coefficient of this current reference is less than 290 ppm/°C over the temperature range from -20°C to 110°C. What's more, it is compatible with standard CMOS technology, which makes its application more flexible.
This work studies the electrical and testing reliability issues of CuxO based RRAM (Resistive Random Access Memory). Firstly, we study the most important electrical reliability issue-data retention capability, and propose a filament/charge trap combined model to clarify the retention failure mechanism. Secondly, we respectively study the reliability problems caused by the SET compliance current in...
In order to calculate the temperature of the phase change memory (PCM) cell, a thermal physical model of the PCM device having Ge2Sb2Te5 (GST) layer has been proposed and demonstrated. By calculating and comparing with the Joule heating of the PCM cell at different programming state between based on the voltage - current curves and based on the formula to calculate temperature, it is found that the...
This paper presents a 8448MHz phase-locked loop (PLL) with a proposed divider implemented in 0.13 μm CMOS technology. Compared with conventional current mode logic (CML) divider, the proposed split-load divider presents wider operating frequency range and lower power dissipation. The ratio of the locking range over the center frequency is up to 70% depending on the operating frequency. It consumes...
An improved mobility model for device simulation is presented. The model is based on charge density instead of effective surface electric field. Compared to the other models, it accounts for substrate bias effect and channel length dependence.
SCMOS is a low cost, high capacity, high speed, high yield, and power saving VLSI device platform technology for microelectronics chips and modules. Benefits include: (1) Uses the complementary Low threshold Schottky Barrier Diodes (LtSBD or simply SBD). (2) Integrated the SBD and CMOS transistor as basic circuit elements for Analog, Logic, and Memory (ALM) macros. (3) Single power supply chip. Circuits...
A systematic computational fluid dynamic (CFD) study was performed to investigate the effects of operating parameters of chamber pressure and wafer carrier rotation rate on the GaAs/AlGaAs deposition rate and uniformity in vertical rotating disc metal organic chemical vapor deposition (MOCVD) reactors. It is shown that significant improvement of the reactors efficiency can be achieved by finding the...
Ultrathin (11 nm) strained SiGe-on-insulator (SGOI) with a Ge fraction of 0.5 was fabricated by Ge condensation technique. The residual compressive strain as high as 1.72% was achieved in SGOI layer by reducing the initial thickness of as-grown Si0.93Ge0.07 layer. Strained-SGOI pMOSFET exhibits a hole mobility of 3 times higher than that of Si-on-insulator pMOSFET.
In this paper the photocurrent properties of the CdS/CdTe thin film solar cell were modeled by using relative physical models that were the incoherence model of the optical generation, the continuity equation for carriers and the current density equation. Then the effect of CdS and CdTe thickness on the photo current was simulated. The results of the simulation show that: a optimum CdTe thickness...
A simple digital background-calibration technique is proposed for a pipelined analog-to-digital converter (ADC). Both gain error and DAC error are measured and calibrated by injecting two uncorrelated pseudo-random sequences into the MDAC. With this method, not only small capacitors might be used, leading to small chip size, but also the traditional current starving high gain op-amps of pipelined...
The specific property of the dual quantum dot transistor is that the current is strongly controlled by resonance tunneling between two quantum states in both dots. The property is analyzed clearly by the method based on Schrödinger equation for an electron in the dot and stochastic theory.
The reverse generation current under high gate voltage stress condition in LDD MOSFET has been studied. It is found that the generation current peak decreases as the stress time increases. It ascribes to the dominating oxide trapped electrons in n-MOSFET and trapped holes in p-MOSFET which reduce the effective drain bias so that lowering the maximal generation rate. The density of the effective trapped...
A smart temperature sensor based on 0.35um ASMC CMOS process with an inaccuracy of ±1°C from -55°C to 125°C is presented. The sensor uses substrate vertical bipolar transistor to measure the temperature and errors resulting from nonidealities in the readout circuit are reduced to 0.1°C level by applying dynamic element matching (DEM) and chopping offset cancellation techniques. By using pseudo-random...
Based on Brokaw bandgap cell, an improved implementation of BGR which consists of a temperature compensated circuit and a simple feedback loop circuit is presented. The circuit exploits a high-order compensation method to realize a low TC and uses an op-amp-avoided feedback loop circuit to save the power dissipation. Implemented in 0.5μm BCD process, the proposed circuit achieves a TC of 1.9 ppm/°C...
In this work we propose a fully experimental method to extract the barrier lowering, at the operative bias point above threshold, in short-channel saturated MOSFETs using the Lundstrom backscattering transport model. At the same time we obtain also an estimate of the backscattering ratio. Respect to previously reported works, our extraction method is fully consistent with the Lundstrom model, whereas...
The single analog filter (SAF) hybrid filter bank (HFB) ADC is presented in this paper. Base on SAF architecture, a calibration model is derived to integrate the analog filter's realization errors and channel mismatches errors. A two-channel SAF HFB ADC with 12-bit resolution and 200MHz sampling rate is implemented. The experimental results show that the average spurious-free dynamic range (SFDR)...
Degradation of electrical characteristics of NdAlO3/SiO2 stack gate under the constant voltage stress (CVS) is presented. It is found that the electron trapping, positive charges and oxide trap generation acts together, which causes the degradation of NdAlO3/SiO2 stack gate. The transport mechanisms of the gate leakage current in NdAlO3/SiO2 stack gate are also investigated. Frenkel-Poole emission...
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