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This paper reports modeling the parasitic bipolar device in the 40 nm PD SOI NMOS device considering the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during transient operations could be modeled. During the turn-on transient by imposing a step voltage from 0 V to 2 V at the gate, the case with a slower rise time shows a faster turn-on in the...
A non-trivial nature of the power management circuit design is emphasized based on three case studies. The events of transient latchup and device failure under Charged Device Model (CDM) pulse due to an unexpected current path in power analog circuits are analyzed demonstrating the value of mixed-mode simulation approach.
In this article, an optimized transient performance CCL-LDO is proposed, which adopts the controlling method of the charge pump phase-locked loop. With 1μF decoupling capacitor, the experimental results based on 0.13μm CMOS process show that the output voltage is 1.0V, and when the workload changes from 100μA to 100mA transiently, the stable dropout is 4.25mV, settling time is 8.2μs and undershoot...
In early days, our project team has analyzed the electric field, threshold voltage, capacitance, cut-off frequency and other characteristics of the double doping polysilicon gate MOSFET (DDPG-MOS), see references. In this study, the process steps of DDPG-MOS are designed and simulated with software TSUPREM. Then the frequency and transient characteristic of the device are analyzed using software MEDICI...
Two numerical simulation techniques are presented to investigate the heating issues in nanoscale Si devices. The first one is the Monte Carlo simulation for both electron and phonon transport, and the transient electrothermal analysis is carrier out in n+-n-n+ device with the n-layer length of 10 nm. The second is the molecular dynamics approach for simulating the atomic thermal vibration in the nanoscale...
The transient effect of graded channel partially-depleted silicon-on-insulator nMOSFETs are analyzed by SILVACO ATLAS software. The switch on and switch off transient behaviors are studied for the device. While the device operates in the kink region, the transient effects of drain current were also investigated. It was found that the transient characteristic of the graded channel device was superior...
A radiation hardened 256K-bit asynchronous SRAM is presented. It is fabricated by a 0.5-micron, radiation hardened CMOS PDSOI process with 3 layers of metal. It features 800uA stand-by current, 42ns access time, 300K rad(Si) total dose tolerant and 1.5 × 1011rad (Si)/s dose rate survivability. A 28-pin DIP package is used. The circuit operates with ambient temperature from -55 to +125°C and power...
The method of using small-signal model to analyze jitter of the clock driver caused by thermal noise is presented. Multi-stage quasi-infinite load differential amplifier structure to effectively achieve low clock jitter is proposed. With transient noise simulation, jitter in the clock driver can be calculated. Through testing the SNR of ADC, The jitter of the designed clock driver in this paper is...
A low-power, capacitor-free low-dropout regulator (LDO) with Pseudo-Input stage feedforward compensation (PISFFC) is proposed in this paper. This novel FFC technique, employing the method of capacitive-coupling to provide large dynamic current for driving power transistor, is highly integrated, widely applicable and can provide ultra-fast load transient response. Compared to conventional slew rate...
With the development of VLSI technology, logic circuits are becoming more and more vulnerable to soft errors due to particle hits. In order to guide reliable logic circuit design, it is important to develop efficient tools for soft error rate estimation. In this paper, we present a framework FAST for accurate SER estimation in logic circuits. FAST models detailed behaviors of transient pulses in logic...
A novel structure of 4H-SiC MESFETs is proposed which focuses on surface trap suppression. A MOS gate controlled spacer layer is shown to improve both DC and AC characteristics due to suppressed surface effect and decreased gate capacitance. A very high power density of 6.1 W/mm is obtained at S band operation. Compare with the well recognized buried gate structure, there is a significant improvement...
A new on-chip CR-based electrostatic discharge (ESD) detection circuit for system-level ESD protection design is proposed in this work. The circuit performance to detect positive or negative electrical transients generated by system-level ESD tests has been analyzed in HSPICE simulation and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed...
We present a reliability analysis of a new vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM applications. The proposed 1T-DRAM device can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved by about 95% when compared to the planer bMPI 1T-DRAM. Owing to the double-gate structure,...
In this paper, the static and dynamic switching characteristics of Ti/HfO2/TiN resistive random access memory (RRAM) have been examined. Based on the experimental results, several pertinent device characteristics can be developed, which include a tunneling barrier width model to explain the RRAM switching behaviors, and the ac transient switching characteristics for circuit model development. We also...
The ASK modulation is widely adopted in wireless communication and also in bio-implanted system. In this paper, a low-power CMOS ASK clock and data recovery (CDR) circuit is designed for cochlear implants based on the proposed monostable circuit under CMOS 0.18μm technology. This monostable circuit has a great robustness and the transient time only differs 5% under 36°C, and behaves just 10% variety...
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