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This paper provides a comprehensive guideline to design high efficient Si thin film solar cells via surface periodic Si nanopillars (SiNP) array texturing. A power conversion efficiency of ~18.1% is predicted to be achievable for the cell consisting of the SiNP array (array periodicity of 500 nm, SiNP diameter of 250 nm, and SiNP length of 1000 nm) on 800 nm thick underlying Si film based on the optical...
A small-granularity solution with high performance and low area cost for fault-tolerant routing of hard error in 2D-Mesh Network-on-Chip is proposed. This solution presents a new fault model, defines separately node-fault and link-fault, reduces situations classified as node-fault effectively, and consequently improves the performance of the network. By defining some new paths to substitute failure...
Plasma immersion ion implantation (PHI) is a very useful technique in the fabrication of silicon-on-insulator and high-k dielectrics and is commercially used to produce shallow junctions in deep-sub micro meter integrated circuits. The applications of PHI are in fact much broader covering many other areas such as metallurgy and particularly biomedical engineering. Many of the innovations and protocols...
Graphene, a two-dimensional carbon form with the highest intrinsic carrier mobility and many desirable physical properties at room temperature, is considered a promising material for ultrahigh speed and low power devices with the possibility of strong scaling potential due to the ultra-thin body. (Fig. 1) [1-3] Here IBM reports progress in graphene nanoelectronics, synthesizing wafer-scale monolayer-controlled...
Nanotube electronics still faces significant challenges such as integration/assembly, co-existence of metallic and semiconducting nanotubes, and air-stable n-type nanotube transistor for complementary circuit operation. Here we report our solutions to these major obstacles, which may eventually lead to realistic and scalable nanotube integrated circuits. We report the wafer-scale synthesis, transfer...
This work presents a preliminary performance comparison between the new and conventional block oxide (BO) bulk-MOSFETs that suggests the proposed BO structure as a candidate for scaling planar CMOS to 16 nm generation and beyond. Also, the combined application of the isolation-last process (ILP) and the BO process provides a method of forming a new BO (NBO) structure that diminishes the short-channel...
In this work, we studied current transport in mono-, bi-and tri-layer graphene. We find that both the temperature and carrier density dependencies in monolayer and bi-/tri-layers are diametrically opposite. These difference can be understood by the different density-of-states and the additional screening of the electrical field of the substrate surface polar phonons in bi-layer/tri-layer graphenes...
The internal gettering (IG) of Cu contamination in Czochralski (Cz) silicon wafers has been investigated using both a conventional IG process based on high-low-high (H-L-H) annealing and a rapid-thermal-process (RTP) based magic denuded zone (MDZ) process. It is found that a denuded zone (DZ) and bulk micro-defects (BMDs) acting as the gettering sites were formed in both cases. However, after cross-sectional...
The 5-nm-thick HfO2 film doped with 35 mol% Gd2O3 (GDH) as a high k dielectric has been epitaxially grown on Si (100) substrate by pulsed laser deposition (PLD). In situ reflection high-energy electron diffraction (RHEED) evolution of the (100)-oriented GDH during the deposition has been investigated and shows that a two-dimensional (2D) single crystalline GDH grows with a smooth surface. The in-plane...
In this work, the properties of sputtered Mo/TaN bilayers and Mo-Ta single layer as diffusion barriers were investigated for Cu metallization. The experimental results show that the Mo(5nm)/TaN(5nm) stack can withstand annealing up to 600°C for 30min and the Mo-Ta(5nm) alloy barrier can effectively prevent Cu diffusion after 500°C annealing.
Silicon nanowire transistor with side-gate and back-gate has been fabricated by electron beam lithography combined with dry oxidation on a doped silicon-on-insulator wafer. The effects of back-gate and side-gate on the properties of single electron transport were investigated by measuring the channel current as function of the applied gate voltages. The tunable single electron effect and Coulomb oscillations...
A new type of crystal seed, polycrystalline Ge (poly-Ge) formed by Co induced crystallization was used in the rapid-melting-growth (RMG) of Ge. With the poly-Ge seed, the grain size of Ge films obtained was significantly larger than the one using single crystal epitaxial Si as crystal seed and the one without any crystal seed. High quality (almost single crystal) Ge was obtained on 1 mm × 1 mm square...
Two numerical simulation techniques are presented to investigate the heating issues in nanoscale Si devices. The first one is the Monte Carlo simulation for both electron and phonon transport, and the transient electrothermal analysis is carrier out in n+-n-n+ device with the n-layer length of 10 nm. The second is the molecular dynamics approach for simulating the atomic thermal vibration in the nanoscale...
The surface passivation properties of hydrogenated amorphous silicon suboxides (a-SiOx:H) deposited by plasma-enhanced chemical vapour deposition (PECVD) have been investigated. The process gases were nitrous oxide and a mixture of silane and helium at a deposition temperature of ~250 °C. Minority carrier lifetimes up to 270 us on 4·Ω·cm p-type float-zone silicon wafers were obtained. With thermal...
An overview of metallic source/drain (MSD) contacts in nanoscaled MOSFET technology is provided in this paper. MSD contacts offer several benefits for nanoscaled CMOS, i.e., extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. In order to achieve high performance MSD MOSFETs, many design parameters such as Schottky barrier...
The review addresses the major challenges that Nanoelectronics will have to face in the next decades. A multifaced strategy is followed to scale down CMOS based technology with new materials and disruptive architectures, heterogeneous integration, alternatives to MOSFET for information processing introducing 3D schemes at the Front End and back end levels.
Reflectance spectrum calculations for a MgF2/diamond-like carbon(DLC)/DLC(or porous silicon (PS) ) silicon triple layer antireflection coating(ARCs) and the nanoporous silicon dioxide (NPSiO2) / DLC/DLC(or PS) triple layer ARCs are performed using the matrix method. The results are compared with the corresponding spectrum of a silicon oxynitride (SiOxNy)/PS, DLC/PS double layer ARCs and some triple...
We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<;10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting <;100> NW channel instead of <;110> NW, Ion = 1 mA/μm for Ioff = 100 nA/μm is achieved...
Resistive switching characteristics of Ag/SiO2/Pt memory cells with different set current compliance are studied. Ag/SiO2/Pt cells with low set current compliances show excellent bipolar switching characteristics after forming, including low operation voltage (<;0.5V), low operation current (~1μA), high resistance ratio (104) and good retention characteristic. Co-existence of bipolar and unipolar...
A fast integrated gate driver with amorphous silicon thin film transistor (a-Si:H TFT) is proposed in this paper. To improve the circuit speed, a new input scheme is designed to provide a full scale pre-charge voltage. So the loss of pre-charge voltage, a challenge in the conventional designs, is avoided. Simulations show that the proposed gate driver has a much improved driving speed in comparison...
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