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RF noise performance of PD-SOI MOSFETs at 40 nm gate length is reported. Using drift-diffusion transport, a good match between small signal measurements and simulations is obtained in presence of velocity saturation and impact ionization. Similar to bulk, PD-SOI also exhibits excess RF channel noise. A sharp rise in the channel noise parameter γ near the kink region in the DC I–V can be explained...
In this paper, we demonstrate high performance Fully Depleted Silicon-On-Insulator CMOS on 300mm strained SOI (sSOI) wafers. Up to 100% drive current (ION) enhancement is demonstrated by sSOI nMOSFETs vs. unstrained SOI at W=80nm active width and L=45nm gate length. These devices indeed yield 1200μA/μm ION at IOFF=10-8 A/μm and VD=0.9V supply voltage. At the same time, they highlight the same excellent...
A workfunction-tuned TiN metal gate is integrated into ultra-low-power FDSOI CMOS transistors, optimized for subthreshold operation at 0.3 V. The workfunction of the TiN metal gate is tunable across the mid-gap range, by adjusting deposition parameters and post-deposition annealing. The transistors show 71% reduction in Cgd and 55% reduction in Vt variation, compared to conventional FDSOI transistors...
Hole mobility in fully-depleted GeOI pMOSFETs is determined and analyzed using for the first time the geometric magnetoresistance technique. The temperature dependent measurements clarify the scattering mechanisms. A significant difference between effective mobility and magnetoresistance mobility is found. Unlike the SOI nMOSFET, this ratio (rMR ≃ 1.8) is rather independent on the temperature and...
An ultra-low-power temperature-sensor-based silicon-on-insulator (SOI) CMOS Integrated Circuit (IC) for harsh environment application is presented. It first detects a temperature threshold, secondly generates a wake-up signal that turns on a data-acquisition microprocessor once the threshold has been detected and thirdly operates as a temperature sensor in a harsh environment while being wired to...
The robustness against Electrostatic Discharge (ESD) events of gated diodes, fabricated in CMOS 45nm FDSOI technology, is compared for 10nm and 145nm Buried Oxide (BOX) thickness. It is shown that the performance of devices for co-design on thin BOX is improved thanks to a better thermal dissipation: A gain of 1.6 on the robustness was found.
This paper presents a new approach to optimize the RF performance at high temperatures for low power low voltage applications. It is shown that the correct choice of the bias point can result in an improvement of the RF behavior of SOI transistors with increasing the temperature, which is opposite to the traditional degradation of RF behavior with increasing temperature. This approach is confirmed...
The compact SOI-MOSFET model HiSIM-SOI based on the complete surface-potential description is presented. The model considers all possible charges induced in the device for the formulation of the Poisson equation, which is solved iteratively. Thus HiSIM-SOI is valid for any structural variations from thick to extremely thin SOI or BOX layers. The dynamic depletion between the fully and partially depleted...
Using a compact model derived for long channels ΠFET, TGFETs and planar FDSOI transistors, it is demonstrated that experimental fully depleted devices can operate in the 'back-interface inversion' regime even at VG2 grounded. As a result, two threshold voltages appear in the transistors, with an experimental difference of threshold voltages up to several hundreds mV for planar FDSOI devices. As a...
This paper analyzes the stability, performance, and variability of 6T FinFET SRAM cells with asymmetric gate-to-source/drain underlap devices. At Vdd = IV, using asymmetric source-underlap access transistors can improve RSNM while degrading WSNM; using source-underlap pull-up transistors can improve WSNM without sacrificing RSNM. Thus, the conflict between improving RSNM and WSNM in 6T FinFET SRAM...
In the last few years, many efforts have been made looking for the improvement of the DC and RF performance of MOS transistors. In this scope, Schottky-Barrier transistors appear as very interesting alternative to conventional devices. In this paper we present the non-linear behavior of dopant segregated n-type SB-MOSFETs with 180 nm channel length.
In this study, we demonstrated that electrolytes in contact with SOI-based back-gated sensors are complexely coupled to applied back gate biases. Because to this, the liquid voltage modulates the top channel and controls the operating point of the device. This dual gating behavior has strong implications on the performance of both nanoribbon and nanowire sensors.
This report shows an analysis of device operation on dynamic depletion mode of SOI MOSFETs, from view points of wide range geometry size, temperature and also considering device physics, second peak of gm, self-heating effect and so on. It is summarized a general picture of DD mode, which is important knowledge for next new compact circuit model.
The successful optimization and characterization of a deep trench isolation in a thick SOI process for operating voltages up to 650 V is reported. Different technologies were investigated to optimize the mechanical stress during wafer processing and to increase the breakdown voltage of a single trench configuration. Comprehensive electrical characterization was done to investigate achievable operating...
Low power design has always been critical to high performance. With the latest technologies, being able to significantly reduce any portion of the overall system power becomes an absolute requirement for extending the lifetime of the system. Clock generation and clock tree distribution are always identified as a significant portion of the power dissipated in a chip. We describe here a servocontrol...
Improvement of current drive in n- and p-type silicon junctionless MOSFETs using strain is demonstrated. The extracted piezoresistance coefficients are in good agreement with the piezoresistive theory and the published coefficients for bulk silicon even for 10 nm-thick silicon nanowires as narrow as 20 nm.
A novel RF SOI LDMOS with buried P-type layer (BPL) was proposed for improvement of its forward block characteristic. The proposed BPL RF SOI LDMOS consists of an additional buried P-type layer inserted between buried oxide layer and N-drift region based on the conventional RF SOI LDMOS structure. When the proposed Device lies in forward block state, the junction across the interface between N-drift...
From the analog performance perspective, there is a fin cross-section shape influence on electric parameters. At weak inversion levels the gm/ID is shape dependent, while for moderate and strong inversions the strain type is dominant, where the mobility starts to play an important role. The output conductance and the Early voltage show a strong dependence on both fin shape and strain type. For thinner...
This work presented the analog behavior of nMOS Junctionless transistors in the temperature range of 100 K to 473 K investigated by experimental results and simulations. It has been shown that gm,max of JL present a parabolic-like dependence on temperature. On the other hand, the JL gm/IDS is nearly insensitive to temperature variations in the on state, which can be interesting for several analog...
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