The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A Ti/TaN multi-layer can achieve a highly reliable Cu interconnect with a porous SiOC (ELK; k <; 2.5) structure. Ti shows good wettability with Cu and unique properties with extreme low-k (ELK)-structured interconnects. On the other hand, Ta is known to be an effective barrier to Cu diffusion. We confirmed that the Ti barrier is different from the Ta barrier from the viewpoint of metal-oxide behavior...
In this paper, two new interconnect technologies designed for integration of a large biosensor array and a signal processing CMOS IC are presented; a TSV technology that can be fabricated in wafers that cannot be aggressively thinned down or have sensitive sensors fabricated in prior processes, and a compliant interconnect technology that enables minimal stress permanent interconnections or low-force...
Wafer-scale three-dimensional (3D) technologies, so-called Wafer-on-Wafer (WOW), beyond post-scaling for high-density integration are discussed. WOW module technologies consisting of wafer thinning, stacking, TSV (Through-Silicon-Via) interconnects, and packaging are described. No degradation for advanced 35-nm SRAM logic and FRAM devices was observed with ultra-thinning below 10-μm for 300-mm and...
Spacer defined double patterning (SDDP) enables further pitch scaling using 193nm immersion lithography. This work aims to design and generate 20nm half pitch (HP) back-end-of-line test structures for single damascene metallization using SDDP with a 3-mask flow. We demonstrated patterning and metallization of 20nm HP trenches in silicon oxide with TiN metal hard mask (MHM).
Impacts of k-value reduction on LSI performances are clarified quantitatively using 2M-gate net-list. Reduction in k-value from 3.0 to 2.5 for M2-M5 interconnect layers achieves 11%-drop in interconnect parasitic capacitance (Cint) and 8.4%-reduction in propagation delay (τd), which also shrinks the effective variability of τd to improve LSI operation margins. From a viewpoint of BEOL fabrication...
With evaluation of various dense silicon-oxy-nitride (SiON) films, a critical density and thickness against to Cu diffusion into Si substrate has been evaluated. Density of SiON films varied with deposition temperature using Plasma-Enhanced Chemical-Vapor-Deposition (PECVD) was ranged from 56% to 69% for bulk film. Cu diffusion increased with decreasing the film density, resulting in 3.5 × 1010 cm...
Phase Change Memory (PCM) technology is demonstrating the capability to enter the broad memory market as a mainstream memory. PCM provides a new set of features, combining components of NVM and DRAM, being at the same time a sustaining and a disruptive technology. In this paper the PCM technology status is reviewed, demonstrating that technology maturity is being achieved. Potential system level usages...
A 40% reduction in W-contact resistance compared to the 45-nm node process has been achieved by using both ALD-TiN treated with N2 remote plasma and B2H6-reduced W-nucleation, and thus the resistance of a 32-nm node W-contact could be kept the same as that of the 45-nm node process despite the 70% shrinkage in the contact diameter. To further shrink devices, low-resistivity CVD-W film was fabricated...
A promising method for controlling sheet resistance (Rs) of Cu interconnect through improved chemical mechanical planarization (CMP) endpoint capability was developed using broadband spectrometry together with feed-forward information from upstream process conditions. With this new method, the wafer-to-wafer (WTW) Rs range was reduced more than 50% compared to time-based CMP polish control.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.