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This study reports the effect of different barrier on Cu interconnect performance. A thin “enhancement” layer of Ru or Co film is deposited between a PVD Ta(N) liner barrier and a Cu seed layer to improve copper to barrier adhesion and copper gap fill. With the enhancement layer of either Ru or Co, no void is found in dual damascene structure with very thin seed. The electrical performance is improved...
CMOS compatible nanowires provide an interesting opportunity to integrate logic functions in interconnects levels. We report here the development of a method to grow silicon nanowire using back-end-of-line compatible copper-based catalysts. Our approach is based on oxidation of copper prior to growth and allows reducing silicon nanowire synthesis temperature below 450°C, a Back-end-of-line compatible...
This paper investigated the plasma ashing damage to patterned porous low k structures with the objective to minimize the plasma damage by optimizing the low-k structural geometry and plasma chemistry. We first extended the plasma altered layer model to formulate the transport kinetics of the plasma process in patterned low-k structures. This enabled us to analyze the effects of the hardmask thickness,...
A process sequence has been developed and characterized to fabricate interconnect structures in MEMS devices capable of withstanding thermal cycles up to at least 700°C. Via test structures with 3-7 μm diameter and 5-10 μm depth were etched in thermally oxidized silicon wafers and filled with platinum (Pt). Key enabling process steps were Pt electroplating and Pt CMP as reported herein. Target applications...
In this paper we report on the use of Silicon wafer to wafer bonding technology using Trough Silicon Vias (TSV) and Cu to Cu hybrid interconnects. We demonstrate that multiple wiring levels of two separate wafers, can be interconnected on a full wafer scale by means of wafer bonding using classical metallization schemes found in IC's such as Al and Cu interconnect technologies. The wafer to wafer...
3D promises a new dimension in composing systems by aggregating chips. Literally. While the most common uses are still tightly connected with its early forms as a packaging technology, new application domains have been emerging. As the underlying technology continues to evolve, the unique leverages of 3D have become increasingly appealing to a larger range of applications: from embedded/mobile applications...
We examine the complex relationship between experimentally-measured power penalty performance metrics of a silicon photonic modulator, and its broad impact on the throughput performance of a full-scale on-chip optical interconnection network. Using our physically-accurate network-level simulation environment, we further evaluate this impact from hypothetical device performance improvements. The results...
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