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CMOS compatible nanowires provide an interesting opportunity to integrate logic functions in interconnects levels. We report here the development of a method to grow silicon nanowire using back-end-of-line compatible copper-based catalysts. Our approach is based on oxidation of copper prior to growth and allows reducing silicon nanowire synthesis temperature below 450°C, a Back-end-of-line compatible...
We have developed networked-nanographite (NNG) wires as the first step for multilayer graphene interconnects. Photoemission-assisted Plasma-enhanced CVD has been proposed as a growth method on dielectrics without catalysts. The activation energy of carrier conduction for NNG wire was almost the same as that of multilayer graphene exfoliated from highly oriented pyrolytic graphite (HOPG). This means...
In this paper, two new interconnect technologies designed for integration of a large biosensor array and a signal processing CMOS IC are presented; a TSV technology that can be fabricated in wafers that cannot be aggressively thinned down or have sensitive sensors fabricated in prior processes, and a compliant interconnect technology that enables minimal stress permanent interconnections or low-force...
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