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This study reports the effect of different barrier on Cu interconnect performance. A thin “enhancement” layer of Ru or Co film is deposited between a PVD Ta(N) liner barrier and a Cu seed layer to improve copper to barrier adhesion and copper gap fill. With the enhancement layer of either Ru or Co, no void is found in dual damascene structure with very thin seed. The electrical performance is improved...
The effects of structural design on the mechanical reliability of Cu/low-k multi-layer interconnects are investigated using finite element method. The Chip Package Interaction (CPI) was analyzed for a model of twelve wiring layers to calculate the energy release rate (ERR). The relations between the feature dimensions, such as copper interconnect width and low-k dielectric thickness, and the interfacial...
Fundamental material interactions as pertinent to nano-scale copper interconnects were studied for CVD Co with a variety of micro-analytical techniques. Native Co oxide grew rapidly within a few hours (XPS). Incorporation of oxygen and carbon in the CVD Co films (by AES and SIMS) depended on underlying materials, such as Ta, TaN, or Ru. Copper film texture (by XRD) and agglomeration resistance (by...
CMOS compatible nanowires provide an interesting opportunity to integrate logic functions in interconnects levels. We report here the development of a method to grow silicon nanowire using back-end-of-line compatible copper-based catalysts. Our approach is based on oxidation of copper prior to growth and allows reducing silicon nanowire synthesis temperature below 450°C, a Back-end-of-line compatible...
We have developed networked-nanographite (NNG) wires as the first step for multilayer graphene interconnects. Photoemission-assisted Plasma-enhanced CVD has been proposed as a growth method on dielectrics without catalysts. The activation energy of carrier conduction for NNG wire was almost the same as that of multilayer graphene exfoliated from highly oriented pyrolytic graphite (HOPG). This means...
Compact modeling and design of spiral inductors and interconnects in RF/mm-wave circuits require accurate yet efficient computation of their impedances. Till date, this task relies on electromagnetic (EM) field solvers with computational expense that does not scale beyond a few individual circuit components. This paper introduces an approach to compute impedances of interconnects and multiple inductors...
We present a methodology for capturing the intrinsic impact of both low-k dielectric stacks and packaging materials on the mechanical integrity of Cu/low-k interconnects. This drastically reduces the time and cost of sample fabrication and reliability tests and provides short-cycle feedback for both low-k and packaging materials development. Furthermore, this methodology is applicable for all types...
This paper investigated the plasma ashing damage to patterned porous low k structures with the objective to minimize the plasma damage by optimizing the low-k structural geometry and plasma chemistry. We first extended the plasma altered layer model to formulate the transport kinetics of the plasma process in patterned low-k structures. This enabled us to analyze the effects of the hardmask thickness,...
A process sequence has been developed and characterized to fabricate interconnect structures in MEMS devices capable of withstanding thermal cycles up to at least 700°C. Via test structures with 3-7 μm diameter and 5-10 μm depth were etched in thermally oxidized silicon wafers and filled with platinum (Pt). Key enabling process steps were Pt electroplating and Pt CMP as reported herein. Target applications...
In this paper, we investigate the electrical behavior of TSV with increasing temperatures (25-150°C). TSV capacitance, leakage current and TSV resistance with varying temperatures are reported. TSV C-V characteristics are analyzed to extract the oxide charges. It is confirmed that the depletion behavior of TSV can be exploited to reduce TSV capacitance even at higher temperatures. In addition, lumped...
In this paper we report on the use of Silicon wafer to wafer bonding technology using Trough Silicon Vias (TSV) and Cu to Cu hybrid interconnects. We demonstrate that multiple wiring levels of two separate wafers, can be interconnected on a full wafer scale by means of wafer bonding using classical metallization schemes found in IC's such as Al and Cu interconnect technologies. The wafer to wafer...
In order to maintain the historical scaling of computational power in information processing beyond the 2020 technology node, switches that are based on state variables other than electron charge are currently being investigated. Examples of alternate state variables include the electron spin, pseudo-spin in graphene, and excitons. This paper discusses different communication mechanisms for on-chip...
Subthreshold circuits have become attractive for various ultra-low power electronic applications. In subthreshold circuits, supply voltage is below the threshold voltage of transistors. This paper discusses both evolutionary and revolutionary interconnect technologies needed to enhance the speed and energy efficiency of subthreshold circuits. It is demonstrated that lowering copper interconnect width...
As porous low k films are integrated for 45nm/32nm and extend into 22nm/16nm technology nodes, there is a need for more rigorous structural design of porous low k films to meet the integration challenges. This paper demonstrates the ability to tune porous low k films and discusses the impact of these choices to subsequent integration steps such as etch, ash and wet clean processes. Balancing carbon...
Cross-point memory structure suffers from a substantial sneak path leakage and a large degradation of output signal due to the parasitic resistance of the interconnects. In this work, we study the parameter requirements of resistive cross-point memory array under the worst case write and read operation. We focus on the pattern dependence of the memory array and compare the effect of resistance values...
The introduction of future technology nodes is accompanied by further downscaling of the interconnect dimensions resulting in the growth of Cu grains with a grain size that is significantly smaller than 100 nm. Consequently, well established techniques for orientation imaging microscopy reach their resolution limit for sufficient Cu microstructure characterization. The only suitable alternative is...
As copper interconnect structures are shrinking with each technology node novel metals other than PVD Ta(N)/Ta are being introduced as barrier materials. These materials act as seed enhancement layers and enable the Cu filling of the narrowest structures. However, the integration of such metals into the manufacturing of sub-35 nm wide Cu lines produces several challenges which need to be addressed...
The high resolution Transmission Electron Microtomography (TEMT) for characterization of grains in a Cu sub-100nm line was firstly reported. A new sample preparation method was developed for obtaining TEM projections from the tilted sample from -90 to +90 degrees. A Cu grain structure was become clear by the 3D TEMT. Furthermore grooving at the surface and micro voids of a few nm were found at the...
The combination of self-formed barrier (SFB) and extreme low-k (ELK) dielectric is an attractive candidate for interconnect integration beyond 28nm-node regarding to low RC delay and Cu filling. Attempt is made to understand the formation mechanism of SFB through combinations with various ELK dielectrics in this study. In terms of wiring and dielectric reliabilities, the combination of MnxOy SFB and...
3D promises a new dimension in composing systems by aggregating chips. Literally. While the most common uses are still tightly connected with its early forms as a packaging technology, new application domains have been emerging. As the underlying technology continues to evolve, the unique leverages of 3D have become increasingly appealing to a larger range of applications: from embedded/mobile applications...
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