Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
In this paper, we study the signal integrity issues of through-silicon-via (TSV)-based 3D IC layouts. Unlike the most existing work, our study reports the coupling noise among all nets and all TSVs used in a real processor design implemented in 3D. Our RTL-to-GDSII design flow consists of commercial tools, enhanced with various add-ons to handle TSV and 3D stacking. Using this tool flow, we generate...
This study reports the effect of different barrier on Cu interconnect performance. A thin “enhancement” layer of Ru or Co film is deposited between a PVD Ta(N) liner barrier and a Cu seed layer to improve copper to barrier adhesion and copper gap fill. With the enhancement layer of either Ru or Co, no void is found in dual damascene structure with very thin seed. The electrical performance is improved...
The effects of structural design on the mechanical reliability of Cu/low-k multi-layer interconnects are investigated using finite element method. The Chip Package Interaction (CPI) was analyzed for a model of twelve wiring layers to calculate the energy release rate (ERR). The relations between the feature dimensions, such as copper interconnect width and low-k dielectric thickness, and the interfacial...
Fundamental material interactions as pertinent to nano-scale copper interconnects were studied for CVD Co with a variety of micro-analytical techniques. Native Co oxide grew rapidly within a few hours (XPS). Incorporation of oxygen and carbon in the CVD Co films (by AES and SIMS) depended on underlying materials, such as Ta, TaN, or Ru. Copper film texture (by XRD) and agglomeration resistance (by...
CMOS compatible nanowires provide an interesting opportunity to integrate logic functions in interconnects levels. We report here the development of a method to grow silicon nanowire using back-end-of-line compatible copper-based catalysts. Our approach is based on oxidation of copper prior to growth and allows reducing silicon nanowire synthesis temperature below 450°C, a Back-end-of-line compatible...
We have developed networked-nanographite (NNG) wires as the first step for multilayer graphene interconnects. Photoemission-assisted Plasma-enhanced CVD has been proposed as a growth method on dielectrics without catalysts. The activation energy of carrier conduction for NNG wire was almost the same as that of multilayer graphene exfoliated from highly oriented pyrolytic graphite (HOPG). This means...
Microelectromechanical systems (MEMS) technology using “back-end of line” (BEOL) processes for CMOS LSIs (called “BEOL-MEMS” technology hereafter) was developed. BEOL-MEMS makes it possible to monolithically integrate MEMS with LSIs. A pressure sensor is successfully integrated with a CMOS LSI, which shows good mechanical reliability and high output-voltage stability. To demonstrate the potential...
We have investigated electromigration process at metal nanojunctions as small as several tens of atoms and found that the elementary process of electromigration in such nanojunctions is the self-diffusion of metal atoms driven by microscopic kinetic energy transfer from single conduction electrons to single metal atoms. We have also shown that metal nanojunctions are stable and can support extremely...
This paper presents an improvement of electrical programmable fuse with dielectric film. By inserting a dielectric film as cap layer combined with self-align silicide block (SAB) process, the program current margin has been extended. This macro has lower program voltage at 2.3V for 8.5μs and can be successfully read out with proper sensing amplifier design.
Compact modeling and design of spiral inductors and interconnects in RF/mm-wave circuits require accurate yet efficient computation of their impedances. Till date, this task relies on electromagnetic (EM) field solvers with computational expense that does not scale beyond a few individual circuit components. This paper introduces an approach to compute impedances of interconnects and multiple inductors...
We present a methodology for capturing the intrinsic impact of both low-k dielectric stacks and packaging materials on the mechanical integrity of Cu/low-k interconnects. This drastically reduces the time and cost of sample fabrication and reliability tests and provides short-cycle feedback for both low-k and packaging materials development. Furthermore, this methodology is applicable for all types...
The enhanced oxidation of Cu on Ru/diffusion barriers was observed. The in-situ X-ray diffraction results reveal that the Cu oxidation can be inhibited by doping C in either Ru adhesion layer or TaN barrier layer. The RuC/barrier becomes more robust with certain amount of C doped in Ru. ALD Cu2O on the RuC substrate was carried out and the effect of C on reduction of Cu oxide was observed.
This paper investigated the plasma ashing damage to patterned porous low k structures with the objective to minimize the plasma damage by optimizing the low-k structural geometry and plasma chemistry. We first extended the plasma altered layer model to formulate the transport kinetics of the plasma process in patterned low-k structures. This enabled us to analyze the effects of the hardmask thickness,...
A process sequence has been developed and characterized to fabricate interconnect structures in MEMS devices capable of withstanding thermal cycles up to at least 700°C. Via test structures with 3-7 μm diameter and 5-10 μm depth were etched in thermally oxidized silicon wafers and filled with platinum (Pt). Key enabling process steps were Pt electroplating and Pt CMP as reported herein. Target applications...
Limited battery power for wireless devices demands improvement in power efficiency while enhancing system performance. Traditional semiconductor scaling faces challenges to meet this requirement. 3D integration of multiple chips using through silicon via (TSV) is one of the technologies that can extend the performance scaling trend. However, the semiconductor industry will need to overcome many technology...
Imec is developing application specific through silicon vias (TSV) technologies for Si thicknesses of 50 and 100μm in wafer level packaging (WLP) area where thin dies are stacked and electrically connected to each other through post CMOS processed TSVs and (micro-) bumps. 3D-WLP TSV flavors are developed using spin-on dielectric polymers as isolation layer. Electrical results of the TSV-connected...
In this paper, we investigate the electrical behavior of TSV with increasing temperatures (25-150°C). TSV capacitance, leakage current and TSV resistance with varying temperatures are reported. TSV C-V characteristics are analyzed to extract the oxide charges. It is confirmed that the depletion behavior of TSV can be exploited to reduce TSV capacitance even at higher temperatures. In addition, lumped...
In this paper, the amorphous phases in the Ti-based barrier layers are identified. More so, X-ray photoelectron spectroscopy (XPS) technique is employed to study its composition.
In this paper we report on the use of Silicon wafer to wafer bonding technology using Trough Silicon Vias (TSV) and Cu to Cu hybrid interconnects. We demonstrate that multiple wiring levels of two separate wafers, can be interconnected on a full wafer scale by means of wafer bonding using classical metallization schemes found in IC's such as Al and Cu interconnect technologies. The wafer to wafer...
In order to maintain the historical scaling of computational power in information processing beyond the 2020 technology node, switches that are based on state variables other than electron charge are currently being investigated. Examples of alternate state variables include the electron spin, pseudo-spin in graphene, and excitons. This paper discusses different communication mechanisms for on-chip...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.