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Moisture induced interfacial delamination failures are often found in a microelectronic package within die attach epoxy and laminate substrate during moisture sensitivity reliability test. In this paper, a piecewise normalization approach is proposed to simulate moisture sensitivity test with both preconditioning absorption and reflow desorption phases. A bi-material model with analytical solutions...
Increasing demand, regarding to advanced 3D packages and high performance applications, accelerates the development of 3D silicon integrated circuit, with the aim to miniaturize and reduce cost. The study of the reliability of the through silicon via and of most critical areas for the emergence of failure remains a major concern. This paper deals with the variation of stress and strain induced in...
Due to the increase of microelectronic assemblies' complexity, the use of FEM simulations has become inescapable either for reliability prediction, or for virtual prototyping or qualification. This article will first describe the main reliability challenges linked to harsher environmental stresses, to new materials, to third dimension. Some examples taken from the current IMS lab studies, will illustrate...
The main objective of this study is to validate the thermomechanical properties of materials used in some electronic components. The improved performance of HgCdTe infrared focal plane arrays requires reliability of the assembly at low temperatures down to 77K. Unfortunately, the thermomechanical behavior of most materials of these components remains to be clarified, particularly in a cryogenic environment...
In this paper, the state-of-the-art results of research and development in wafer-level packaging (WLP) is reviewed. The paper starts from the introduction of several fan-in wafer-level packaging technologies. The focus is given on the fan-in WLP reliability performance as related to the structural differences. New failure mechanisms that appear in build-up stack layers are discussed. Next, emerging...
As the market demand of high power, high frequency and high efficiency, the advanced RF power packaging and assembly technology is facing the challenge of new material and new design. Improving the thermal conductivity of the heatsink (flange) is one of the effective ways to obtain low thermal resistance (Rth) component. Compared to the silicon transistors, the low-cost, high thermal conductivity...
A dynamic substructural method (DSM) is developed to simulate the board level drop test of a wafer level chip scale package (WL-CSP). Parametric study on package location at the test board, printed circuit board (PCB) thickness and WL-CSP package thickness is conducted in the board level drop test simulations. The peeling stress and first principle stress of the solder joints are checked and discussed...
Summary form only given. The ever increasing complexity and function integration of microelectronic products in combination with the decreasing design margins, the decreasing time-to-market, and ever increasing gap between technology advance and fundamental knowledge opposes a severe challenge for the microelectronics industry to meet the quality, robustness, and reliability requirements of their...
The trends of 3D integration and System-in-Package (SiP) require the adaptation of target preparation methods for failure analysis of these complex integrated devices. Recent improvements in laser-based target preparation make laser cross-sections through several stacked silicon dies possible with remarkably small visible Heat-Affected Zones (HAZs). The distinct removal of Molding Compound (MC), silicon...
Experimental drop test results of 2nd-level assemblies can be influenced by numerous impact factors. The explicit definition of drop testing conditions by the JEDEC standard JESD22-B111 was intended to create a highly repeatable, and thus comparable, experimental setup. Recent developments showed, however, shifting failure modes from component to PCB side. Comprehensive drop tests were executed with...
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