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One major issue in the design of multi-core systems is scheduling execution threads on the many cores. Heterogeneity complicates the issue given the different types of cores with various functionality and power requirements. In a large multi-core chip with long interconnect latencies, minimizing thread migration costs is essential in minimizing the power consumption and maximizing performance. In...
It is critical for the network-on-chip in embedded multi-core and many-core chips to be scalable while limiting power consumption. With the router power dominating the network's power, one way to achieve this goal is by the design of on-chip interconnection networks with small diameters and simple routing. Herein, we present a few new unicast on-chip networks for interconnecting the cores with diameters...
On-chip interconnection networks (OCINs) in many-core systems are key to the system's performance scalability. OCIN design constraints are governed by power, cost, latency, ease of routing, as well as others. As chips with 16 cores are around the corner, we focus on 16-core systems and consider 9 OCINs for 16-core MPSoCs. A key requirement of real time embedded systems is dependable timeliness. This...
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