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The operation of inverters, fabricated in a 1 ??m partially depleted SOI CMOS technology is investigated from room temperature down to liquid helium. It is demonstrated that the transfer characteristics suffer from the floating-body anomalies, like the kink and the breakdown/latch behaviour. Additionally, at 4.2 K, hysteresis, which is related to the cryogenic (freeze-out) behaviour of the n-MOSFETs...
This paper reports on an efficient methodology to optimise conventional channel and Pulse Shaped Doping profile (PSD). We clarify the different physical phenomena responsible of leakage current increasing, then we compare and discuss the impact of the optimised profiles on device performances in term of current drivability, Drain Induced Barrier Lowering (DIBL), mobility and speed considerations.
The hot-carrier (HC) reliability of various interlayer (ILD) and intermetal (IMD) dielectric stacks has been studied on nMOSFET's of a 0.5-μm TLM CMOS process. A phosphosilicate glass (PSG) layer in the ILD strongly suppresses the enhanced HC degradation associated with the spin-on glass (SOG) used for planarization in the IMD. The diffusion barrier properties of the PSG effectively reduce hot-electron...
The hot-carrier-reliability of pure and nitrided tiin gate-oxides (8nm-thick) for p-MOSFET's is investigated with DC stress experiments. A peculiar degradation mode is observed in these 8nm-thick gate-oxides where reducing the channel-width enhances a turn-around phenomenon observed in the degradations of the transistor parameters. This effect is explained by the field-assisted detrapping of electrons...
We propose here a back junction SiGe PMOS structure having a cross section of Poly/SiO2/Si-cap/SiGe/n-epi/p-substrate. The electrical coupling between the front gate and the back p-substrate/n-epi junction reduces the vertical field, thus improving the hole confinement and the SiGe channel mobility, resulting in an improved effective channel mobility. Numerical simulation shows that the back junction...
The first SiGe p-MOSFETs with triangular Ge profiles, fabricated in a Si CMOS-compatible LOCOS isolated process are reported. The feasibility of triangular profiles with peak Ge mole fractions as high as 50% is demonstrated for both CVD and MBE MOSFETs. The transconductance of 3 ??m devices with 0-40% Ge profiles is 34 mS/mm, 100% higher than that of the corresponding Si p-MOSFET fabricated on the...
A characterization of the low frequency noise of Si MOS devices from a 0.35 μm CMOS technology after uniform gate stress and nitridation step is presented. It is found that stress alters noise spectra differently depending on the device area. The spectra can be increased uniformly or may be distorted after stress, indicating a net creation of interface traps. On the other side, nitridation is found...
The low-frequency (LF) noise behaviour of Silicon-on-Insulator MOSFETs fabricated in different SOI CMOS technologies is reported. It is shown that the kink-related excess LF noise, typical for the floating operation of partially depleted transistors can be eliminated by a proper choice of technology, i.e., either by using a fully depleted technology, or so-called dual-gate (gate-all-around) structures...
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