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In this work a review of the basic concepts of recently developed two-dimensional profiling techniques is given. The methods are based on spreading resistance measurements, atomic force surface topography and transmission electron microscopy. The use of spreading resistance for two-dimensional profiling has been introduced three years ago. In the mean time the experimental procedure and the interpretation...
The polarization of light emitted by hot-carriers in silicoin MOSFETs and special purpose test structures is analyzed by meanis of spectrally resolved polarization measurements. The experiments show a siginificant dependence of polarization on the structure and composition of the materials covering the emission area. The results demonstrate that the polarization of hot-carrier light in MOSFETs cannot...
A new GaInP-GaAs HBT technology is proposed in which a thin GaInP layer (40 nm) is used both as the emitter and as a passivation layer of the base. High DC current gain up to 40 are obtained, for a high C doping level (6 1019 cm??3) in the base. The GaInP passivation is demonstrated with the achievement of the same DC current gain for small and large devices with emitter-base junction area of 16 to...
A high performance and low cost complementary bipolar technology has been developed for the realization of higlh-precision, hiigh-frequency, and high voltage analog circuits. The technology, referred to as VIP-3H (Vertically Integrated PNP-3H), offers polysilicon emitter transistors with BVceo of NPN and PNP transistors greater than 85 and 95 volts, respectively. The ft of the NPN is 2 GHz and for...
This paper reports an investigation of non-ideal base currents in epitaxial base (Si or Si1-xGex) bipolar transistors fabricated using a single-polysilicon self-aligned technology. Two independent leakage components are identified. Their spatial and physical origins are used to outline the main critical fabrication steps of this technology.
A new technique for the measurement of lateral junction distances under masking layer edges is described. The method is based on automatic electrical probing of special resistor bridge structures on-chip, and creates a large and statistically significant database from which high resolution measurements of lateral junctions down to 50nm can be extracted with high confidence. Results, data analysis,...
This paper will describe the characterization and electrical optimization of a high performance Atomic Layer Engineered Sealed Interface Local Oxidation (ALESILO) field isolation process steps. This process uses a vacuum load-lock equipped cluster vertical furnace (fig. 1). That allows perfectly controlled nitride/silicon interface sealing avoiding any extra RTN step[1] to achieve 100 nm range bird's...
The effect of silicidation schemes on interface contact resistance has been examined. Evaluation of conventional process (pre-formed junctions), pre-amorphization process, and concurrent process (with silicidation and junction formation at the same time) impacts on interface contact resistance are presented. It is found that preamorphization process using Ge improves the CoSi2/Si contact resistance...
This paper reports a comparison between three designs of p-channel MOSFETs processed with n+ doped polysilicon gates. Two new techniques to reduce DIBL of buried channel pMOSFETs are proposed and compared with a conventional approach. Criteria for this comparison are the short channel effect control, the off-state leakage current, the holding voltage and the saturation drain current. Based on extensive...
We propose here a back junction SiGe PMOS structure having a cross section of Poly/SiO2/Si-cap/SiGe/n-epi/p-substrate. The electrical coupling between the front gate and the back p-substrate/n-epi junction reduces the vertical field, thus improving the hole confinement and the SiGe channel mobility, resulting in an improved effective channel mobility. Numerical simulation shows that the back junction...
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