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We show that a remarkable threshold shift ??Vp and an increase in the saturation current ??Ids can be observed in AlGaAs/InGaAs PM-HEMT's submitted to high temperature (100??C - 200 ??C) storage or hot-electron stresses for relatively short times (about 20 hours). An increase in Ids up to 40% has been observed. The increase is not permanent and can be recovered by a room or low temperature storage...
The volume degradation features of very thin tunnel oxide layers will be deeply analyzed and the validity of the following issues will be demonstrated quantitatively: i) only negative charge builds-up in the bulk of the insulator layer, ii) for a given oxide thickness and gate stress polarity breakdown occurs as soon as the negative trapped bulk oxide charge density attains a critical value, iii)...
The impact of reduced polysilicon doping concentration Np on circuit performance is analyzed using a new polysilicon depletion model. SPICE simulations of inverter chains with different loadings predict that higher circuit delays are expected as Np is reduced. The performance degradation gets compounded when the gate oxide thickness tox is reduced, and/or substrate concentration Nb is increased. For...
In this work we have studied and compared the effects produced by prolonged application of bias-stresses with high source-drain voltage and negative gate voltages in two types of polysilicon thin-film transistors. Two main effects induced by bias-stressing have been observed: off-current reduction and transconductance degradation. The latter effect appears to be strongly related to gate leakage current...
The hot-carrier (HC) reliability of various interlayer (ILD) and intermetal (IMD) dielectric stacks has been studied on nMOSFET's of a 0.5-μm TLM CMOS process. A phosphosilicate glass (PSG) layer in the ILD strongly suppresses the enhanced HC degradation associated with the spin-on glass (SOG) used for planarization in the IMD. The diffusion barrier properties of the PSG effectively reduce hot-electron...
The hot-carrier-reliability of pure and nitrided tiin gate-oxides (8nm-thick) for p-MOSFET's is investigated with DC stress experiments. A peculiar degradation mode is observed in these 8nm-thick gate-oxides where reducing the channel-width enhances a turn-around phenomenon observed in the degradations of the transistor parameters. This effect is explained by the field-assisted detrapping of electrons...
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