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Biased polysilicon field plates [1] are used to achieve 800-V wiring in a typical junction isolated, high voltage integrated circuit. The field plates are biased by phosphorous doped polysilicon resistors, connected in a voltage division scheme to the high voltage wire. The effect of using doped (as opposed to undoped), polysilicon resistors on field plate potential distribution is investigated. It...
The impact of reduced polysilicon doping concentration Np on circuit performance is analyzed using a new polysilicon depletion model. SPICE simulations of inverter chains with different loadings predict that higher circuit delays are expected as Np is reduced. The performance degradation gets compounded when the gate oxide thickness tox is reduced, and/or substrate concentration Nb is increased. For...
Anomalous increase in Vts (NMOS Vt roll-up effect) with the decreasing gate length in sub-micron technologies is usually attributed to the lateral redistribution of doping near source and drain junctions, or to silicon interstitial capture in gate oxide. Our results demonstrate that the poly-Si gate doping level dominates the observed Vt rollup effect and suggest a simple method for its suppression.
This paper describes a method for extracting the bandgap narrowing in the base of Si homojunction or Si/Si1-xGex. heterojunction bipolar transistors from the temperature dependence of the collector current. The method is applied to a Si homojunction transistor with a 6 ?? 1018 cm??3 epitaxial base, and a doping-induced bandgap narrowing of 39meV is obtained. The method is also applied to a Si/Si0.84...
A high performance and low cost complementary bipolar technology has been developed for the realization of higlh-precision, hiigh-frequency, and high voltage analog circuits. The technology, referred to as VIP-3H (Vertically Integrated PNP-3H), offers polysilicon emitter transistors with BVceo of NPN and PNP transistors greater than 85 and 95 volts, respectively. The ft of the NPN is 2 GHz and for...
HBT layers have been fabricated using a multi-step process in a single run. They were made in a new, single-wafer, 200 mm compatible, cold wall UHV-CVD reactor [1]. Preliminary electrical measurements on fabricated transistors demonstrate excellent control of layers thickness and doping transitions which allows to compare these HBT layers with those fabricated by MBE [2] or hot-wall UHV-CVD [3].
The first systematic study of p-Si1-xGex/Si multiple quantum well infrared detectors (QWIPs) grown by low pressure vapour phase epitaxy (LPVPE) is described. The inclusion of undoped Si1-xGex spacer layers adjacent to the p-doped alloy reduces the weakly temperature-dependent ``tunnelling'' component of the dark current. The peak wavelength in the photoresponse spectrum is tuned between 7.2-10.2??m...
Low temperature polysilicon thin film transistors suitable with active-matrix applications are elaborated. Electrical performances can be significantly improved by using a lightly in-situ doped drain. OFF state current can be reduced more than a decade for low drain voltage (Ids ?? 10 pA for Vds ≪ 1 V) in comparison with a heavily in-situ doped drain. Consequently, ON/OFF state current ratio is much...
A novel high gate barrier (HGB) AlInAs/GaInAs/InP HEMT structure is proposed, which overcomes gate leakage current problems due to limited Schottky barrier height in common HEMT design. Gate leakage is a major contribution to low-frequency noise besides deep trap re-charging (1). The crucial point in the novel HEMT design is the insertion of an additional shallow p+-?? doped plane below the gate contact...
Controlled sub-nm oxide growth on (100) silicon wafers in a controlled, O2 containing ambient of a LPCVD-polysilicon deposition clustertool is demonstrated. As a comparison, a conventional LPCVD-polysilicon deposition furnace is used which generates a sub-nm oxide during loading the wafers into the heated furnace. For the first time results for different substrate doping levels are presented. Applications...
A new method for the obtaining of thin oxynitride insulator is described: a nitrogen doped silicon layer is used as a nitrogen atoms source for the nitridation of a buried oxide layer. Capacitor structures are made and electrical characterization by C(V) and I(V) of the oxynitride films are presented and analysed.
Double quantum well with ??doped lattice-strain GaAs/InGaAs/GaAs pseudomorphic heterostructures have been fabricated for the first time. Very high carrier density of more than 1??1013cm??2 along with enhanced mobility of 2100 cm2/vs at 300K are achieved. Influence of barrier thickness on the carrier densities and mobilities are also investigated.
CMOS SOI devices, realised on very thin silicon film on SIMOX material, are very attractive for ULSI application. There are many advantages over bulk that have been frequently emphasised in the literature [1]. For sub-quarter micron devices, there are several candidate architectures and device operations, depending on the gate material: - enhancement mode Partially or Fully Depleted devices, for a...
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