The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The aim of this paper is to present the numerical simulation of the influence of the SALICIDE (self-aligned silicide) process on MOSFET (metal oxide semiconductor field effect transistor) technology. First, we report on the geometrical effects which appear during the growth of the titanium silicide (TiSi2) layer over Si-poly gate. Then, silicidation over boron doped source/drain shallow junctions...
The Monte Carlo simulator IMSIL [2] has been extended to take arbitrarily shaped 2-D structures into account. The lateral dose distribution at a mask edge is studied and compared with lateral SIMS measurements. The lateral dose distributions for boron and arsenic in amorphous and crystalline silicon are compared.
We have verified the design of latchup-free bulk CMOS devices for operating temperatures up to 525K by simulation and measurement using a 1.0 micrometer twin tub ASIC process with epitaxial layer. It is possible to achieve an increase in holding voltage with rising temperature by applying design precautions. A special ASIC cell library for high temperature circuit operation has been developed and...
The impact of reduced polysilicon doping concentration Np on circuit performance is analyzed using a new polysilicon depletion model. SPICE simulations of inverter chains with different loadings predict that higher circuit delays are expected as Np is reduced. The performance degradation gets compounded when the gate oxide thickness tox is reduced, and/or substrate concentration Nb is increased. For...
Constructive Solid Geometry (CSG) is a solid modeling technique widely used for the design of semiconductor devices. With the simulation domain subdivision algorithm presented in this paper, the minimal number of solid modeling operations is required in order to build a three-dimensional (3D) device structure. The algorithm is based on a drawing method which combines information on photolithographic...
Crucial polysilicon-related process steps in high performance bipolar technology are simulated successfully. The forming of a shallow graft base by boron self-aligned outdiffusion from a base-polysilicon film and arsenic outdiffusion from an emitter-polysilicon layer has been studied. Therefore, a two-dimensional simulation model for dopant diffusion in polysilicon has been developed, which includes...
In this presentation the NEWSSTAND network is outlined which has been established as a part of the Human Capital and Mobility Programme funded by the EU. Within NEWSSTAND, major semiconductor research centers and companies are active. The network partners combine their individual expertize in order to promote the progress in the field of semiconductor process and device modeling and simulation. Network...
In this paper, we present a novel electrostatic discharge (ESD) protection device which is, against the catastrophic ESD attack, activated as either a reverse-biased punchthrough bipolar junction transistor (BJT) or a forward-biased diode, depending on the polarity of the input pulse. Experimental data show that the new device is more efficient and area-effective than any other conventional one. It...
Thermal annealing of dopants implanted in silicon devices causes redistribution of the implanted profiles. Increasingly this redistribution occurs in a non-equilibrium regime driven by annealing of implant damage. It affects devices in a variety of ways, from threshold variation to deviations from coded length to catastrophic merging of separate profiles. Predictive modeling of modem device profiles...
A methodology to include cost and yield estimation in a comprehensive TCAD model of semiconductor processing is presented. The underlying idea is that a process recipe used to drive TCAD simulators contains a complete set of information about the process. If it is combined with empirical equipment data, a set of models can be constructed to describe cost as a function of the process recipe and equipment...
We present a study of vertically-grown Si ultra-short FET's based on a new implementation of the Cellular Automata simulation. The probabilistic scattering rates for the electric field have been replaced in the cellular automaton by a new deterministic scattering rule in a fully three-dimensional momentum-discretization, leading to a significant suppression of statistical errors. We have also developed...
In small Si bipolar transistors (BJTs) the sidewall effects play an important role. Extensive device simulations on Si/SiGe/Si heterojunction bipolar transistors (HBTs) and Si BJTs show that in the HBTs the sidewall current injection is strongly suppressed. Consequently, the current gain in the HBT keeps constant down to a much smaller emitter width (We ?? 0.20 ??m) than for a conventional Si transistor...
An analytical DMOS model for circuit simulation based on a subcircuit approach is extended for a variable number of cells. The subcircuit itself consists of a minimal number of elements whose models are physically based and optimized for the special DMOS structure. The DC-description is continous (smooth transitions between the different operating regions of the device), the AC-description is charge...
Vertical bipolar transistors are added to CMOS processes in order to obtain superior analog and drive capabilities. If these transistors can be isolated, special applications like low-voltage designs for battery-operated circuits or amplifier designs for sensors become possible. We report on a modular 40 V BiCMOS process where junction-isolated vertical npn and pnp transistors have been added for...
New experiments on short-time diffusion of gold in silicon are presented. Diffusion of gold in silicon is investigated in the temperature range of 900??C to 1100??C. The values of the barrier energies for both the gold-point defect reactions and the Frenkel pair reaction have been determined as EAu/I = 0.482eV, EAuI/V= 0.971eV, and EI/V = 0.30eV.
A new procedure for realistic calibration of dopant diffusion models to SIMS data for thin doped Si and SiGe layers has been achieved by bringing model data into a form appropriate for direct comparison with measured SIMS and so separating the genuine diffusion broadening from instrumental effects.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.