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Multilevel metallization is a key process for the technology generations below 0.5μm. As the design rules are going smaller, the limits of the classical SOG Etch-Back process are reached in terms of process complexity and long distance planarization. The solution to this problem is to use a Chemical Mechanical Polishing technique for the dielectric planarization. In this paper, we will demonstrate...
This paper describes an approach to the major issues of Design for Manufacturability (DFM) based on Principal Component Analysis and Design of Experiments techniques, which has been formulated and implemented for a 1??m CMOS technology, culminating in the generation of realistic nominal and worst-case model parameter sets.
The impact of reduced polysilicon doping concentration Np on circuit performance is analyzed using a new polysilicon depletion model. SPICE simulations of inverter chains with different loadings predict that higher circuit delays are expected as Np is reduced. The performance degradation gets compounded when the gate oxide thickness tox is reduced, and/or substrate concentration Nb is increased. For...
The feasibility and the limitations of ultra-low-power CMOS technologies are investigated using process and device simulation, followed by post-processing of the simulated IV data. On the basis of simplified modern state-of-the-art processes and special scaling a set of possible ultra-low-power CMOS processes was developed and analyzed for their performance on the gate level.
For a 0.35 μm CMOS technology, an optimized poly buffered LOCOS process is necessary in order to meet the design rules. In this paper, the feasibility of this isolation scheme is demonstrated.
A high performance 0.35 μm CMOS technology is presented for low operating voltages. The increased reliability margin at low supply voltages was used to scale the gate oxide thickness and optimize the channel and source/drain junctions profiles. The resulting well controlled short-channel behaviour of the devices was used to obtain low leakage current at low threshold voltages. Good circuit performance...
DUV excimer based imaging appears to be one of the best candidate for printing subhalf micron devices. In this paper we have investigated the potentiality of such a technique to process 0.35 μm CMOS devices with 3 levels of metallization. Depending on the level to process, positive or negative tone chemically amplified resists have been used. The processing conditions as well as exposure and focus...
A characterization of the low frequency noise of Si MOS devices from a 0.35 μm CMOS technology after uniform gate stress and nitridation step is presented. It is found that stress alters noise spectra differently depending on the device area. The spectra can be increased uniformly or may be distorted after stress, indicating a net creation of interface traps. On the other side, nitridation is found...
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