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Coordinate rotation digital computer (CORDIC) based digital signal processing has become an important tool in consumer, communications, biomedical, and industrial products, providing designers with significant impetus for porting algorithm into architecture. Unfolded implementations of CORDIC algorithm can achieve low latency for rotation and various functions such as division, multiplication, logarithmic...
This paper presents the designed obstacle avoidance program for mobile robot that incorporates a neuro-fuzzy algorithm using Altera?? Field Programmable Gate Array (FPGA) development DE2 board. The neuro-fuzzy-based-obstacle avoidance program is simulated and implemented on the hardware system using Altera Quartus?? II design software, System-on-programmable-chip (SOPC) Builder, Nios?? II Integrated...
The paper presents a novel methodology to implement resource efficient 64-bit floating point matrix multiplication algorithm using FPGA. Approach uses systolic architecture using four processing element (PE's) that gives tradeoffs between resource utilization and execution time, results in reducing the routing complexity for dense matrix multiplication problems.
The computation of shortest path for a mobile automaton between two points in the plane is considered in this paper. An architecturally-efficient solution based on Dijkstra's algorithm is presented for this problem. Results of implementation in Xilinx FPGA are encouraging: the solution operates at approximately 46 MHz and the implementation for a graph with 64 nodes and 88 edges fits in one XCV3200E-FG1156...
Most reconfigurable processors are not fully controlled by software; they are reconfigured using hardware description languages. By moving the data paths into the processor, the system architect can discard the external control logic, the finite state machines and micro-sequencers. Examples for such a processor are the members of the Stretch family, Software Configurable Processors which have a reconfigurable...
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