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60 GHz LNA/PAs, phase shifters (PS), combiners and switches were designed for integrated phase array in CMOS. These components achieved the best known power consumption and size compared to previous publications reported, as a result of the methodology flow and layout optimization that was developed for 60 GHz designs. The extensive use of passive architecture together with the compact layout will...
A beyond 60 GHz cross-coupled NMOS differential LC CMOS VCO is presented in this paper, which is implemented in 45 nm standard CMOS technology. Working with a supply voltage of 1.2 V the circuit draws a current of 38 mA (72 mA including output buffer) and requires a circuit area of 0.037 mm2 including the differential output buffer without pads. The circuit delivers an output power of -9 dBm to -11...
A push-push VCO with embedded balun and resistive CML divider for 60 GHz heterodyne transceiver architecture, are presented. The measured VCO second harmonic output frequency is ~44.6-50[GHz], i.e. ~11.4% tuning range. The phase noise at 1[MHz] offset from the carrier, is ranging between -109 to -112[dBc/Hz] and -97 to -100 [dBc/Hz], for f0/2 and 2 ?? f0 outputs, respectively. The circuit works from...
This paper presents a voltage controlled phase shifter in a 0.25 ??m SiGe BiCMOS technology for 60 GHz applications. Vector combination technique is adopted in phase shifter core. Continuous 360 degree phase tuning from 40 GHz to 70 GHz has been measured. The insertion gain of the complete test circuits is 4.6 dB and that of the phase shifter core is 7.6 dB. The phase shifter is best suited for 60...
This paper presents a high-speed 4 bit full-flash analog-to-digital converter with a new parallel reference network for an UWB radar. The ADC is implemented in 190 GHz SiGe BiCMOS technology, has more than 6 GHz effective resolution input bandwidth and operates up to 16 GSample/s. Power dissipation is 1.15 W including test buffers and 750 mW of the converter itself.
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