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Reducing off-chip bus power consumption has become one of the key issues for low power system design. Although methods have been proposed to reduce the power dissipated in parallel buses, these techniques do not apply to serial communication since they work on consecutive data words. The data line in synchronous serial communication is a major source of power dissipation, apart from the clock line...
Networks-on-chip (NoCs) can improve the communication bandwidth and power efficiency of multiprocessor systems-on-chip (MPSoC). However, traditional metallic interconnects consume significant amount of power to deliver even higher communication bandwidth required in the near future. Optical NoCs are based on optical interconnects and optical routers, and have significant bandwidth and power advantages...
As technology scales, leakage power shares a dominant part in the total power dissipation of the chip and reaches up to 50% or even higher at elevated temperatures in 45 nm technology. Leakage power dissipation is especially problematic for FPGAs due to their reconfigurable nature and large number of inactive resources. Body biasing is an efficient technique to reduce leakage current which has been...
In this paper, a novel low phase-noise and wide tuning-range CMOS differential voltage-controlled oscillator (VCO) for a frequency DeltaSigma modulator (FDSM) is presented. The VCO which converts an analog input voltage to phase information is based on a differential ring oscillator with modified symmetric load and a positive feedback in the differential delay cells, combined with a new bias circuit...
Increasing on-chip power densities with aggressive technology scaling has led to a low-power FPGA fabric with dual supply voltages. Such low-power techniques coupled with the heterogeneity of components on a FPGA have led to non-uniform aging of components due to temperature and voltage dependent failure mechanisms. In this paper, we present techniques in placement and routing stages of the design...
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