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Since lead was banned from the solder joints, mechanical tests of microelectronic components and modules have gained much importance not just in mobile electronics but quite in general. The standardized JEDEC drop test is commonly used. It delivers repeatable results for a wide range of loads in the components mounted on the well specified test PCB. As yet the JEDEC drop test is time consuming and...
The board level drop test is intended to evaluate and compare the drop performance of surface mount electronic components. The JEDEC standardize for board level drop test address test board construction, design, material, component locations and test conditions etc. However, in actual drop test conditions, continued drops usually loosen up the mounting screw, which is not considered in JEDEC. This...
This investigation is aimed at the stability of press-fit interconnections for MID. Moulded interconnect devices (MID) are 3-dimensional substrates produced by thermoplastic injection moulding for large-series applications. The assembly process of press-fit interconnections has been correctly modelled with a FE-Software. With this model the behaviour of the mechanical contact pressure, which decreases...
Interface fracture properties are increasingly requested in electronic packaging, be it for design problems or reliability issues. We demonstrate an induced delamination of the epoxy molding compound and die silicon interface, and propose a mixed mode chisel testing setup (MMC) and its experimental procedure. The MMC addresses several drawbacks of existing methods. The work includes samples from package...
The scope of the paper is to present the result of combining experimental and simulation methodologies to determine mechanical material properties at high strain rates. Miniature bulk specimens which have a diameter comparable to BGA joints are used in the experiments. Stress-strain data recorded at high strain rates proof the high resolution capability of a novel tensile setup. A FEM model of the...
Multi-physics multi-scale modeling issues in various stages of the LED manufacturing, 3D-SiP, and nano interconnects have been discussed. Molecular dynamics (MD) and finite element method (FEM) have been used to study the scale effect of the material properties and the prediction of the module behaviors which are critical to LED fabrication. We propose a new concept to integrate multi-physics/multi-scale...
This work will present case studies of three types of flexible printable circuits subjected to different loading conditions in order to evaluate their technologies regarding mechanical reliability. Typical causes of failure in electronic devices are associated with mechanical stress, moisture, heat from transportation and field use. Typically manufacturers carry out tests to evaluate the reliability...
In this paper, a leading indicators based approach has been developed for prognostics and health monitoring of electronic systems. The approach focuses on the prefailure space and methodologies for quantification of damage progression and residual life in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Traditional health monitoring...
Embedding of discrete semiconductors into substrates has the advantages of achieving high degree of miniaturization, good electrical performance and possible low cost. A MOSFET power package based on the embedded die technology was developed and the demonstrators were built. To reduce cost and time-to-market, thermo-mechanical virtual prototyping is applied to support the package development. 2D and...
Flexible substrates (polymers) for plastic electronic products are far less stable to environmental factors, like heat and moisture, than currently used non-flexible substrates (silicon). This introduces problems during the lithography process of these products. This study presents a thermo-mechanical model of PEN foil; an organic material often used as flexible substrate for plastic electronics....
In this paper we discuss the influence of solder joint geometry on the lifetime of a flip chip assembly. Geometry variations caused by variations of solder volume, pad configuration, and pad size on the printed circuit board (PCB) were taken into account. Typically these parameters vary due to technological fabrication tolerances. Consequently, the influence of such design aspects on system reliability...
The bump on flexible lead (BoFL) is a chip-to-substrate interconnect technology which uses flexible structures to accommodate the CTE mismatch between the chip and PCB substrate and consequently should be reliable without underfill. To achieve a high flexibility, the lead-free bump is located on a flexible lead. The flexible lead consists of a copper redistribution layer (RDL) embedded in a polyimide-bridge...
This paper presents in details the fatigue life prediction models developed for lead-free assemblies in harsh environments during the 3-year European LIFE project GEAMCOS. The approach uses advanced finite element modelling as well as experimental fatigue data. It is also based on a complete material characterisation for a wide range of stress conditions. It focuses on the most critical packages of...
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