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To maximize the design efficiency of the test chip area and maintain the high accuracy measurement requirement of resistors and capacitors, a 4K-cells resistive and charge-base capacitive test structure array is designed for CMOS logic process development, monitor and model. The test chip utilizes 4-terminal (one of 4 is strongly grounded) Kelvin force/sense measurement for resistive-type and charge-base...
This paper presents a method for measuring the complex permittivity of dielectric material on a dielectric/metal stack. A series of circular capacitor and transmission line test structures are designed and fabricated. The methodology has been verified by measuring the dielectric constant of a known SiO2 layer using Capacitance-Voltage (C-V) measurement and scattering parameter (S-parameter) measurements...
In this paper we show a self-consistent methodology to characterize the stress-induced mobility variation in silicon-based devices. The synergy among different experimental techniques (the application of an external mechanical stress and the measure of the process-induced stress), theoretical calculations (based on the finite elements method and the band structure calculation), and silicon validation...
For the first time, an efficient methodology to accurately characterize the gate-bulk leakage current (Igb) and gate capacitance (Cgg) of PD SOI floating body (FB) devices was proposed and demonstrated in 40-nm PD SOI devices with ultra-thin oxide EOT 12 A. By applying the RF testing skill for the proposed SOI test patterns, we can eliminate properly the parasitic elements due to the co-existence...
This paper discusses application of direct charge measurement (DCM) on characterizing on-chip interconnect capacitance. Measurement equipment and techniques are leveraged from Flat Panel Display testing. On-chip active device is not an essential necessity for DCM test structure and it is easy to implement parallel measurements. Femto-Farad measurement sensitivity is achieved without having on-chip...
We describe the development and use of various test structures for 32 nm yield enhancement. These DC defect test structures are tested in parallel mode on a functional tester using special V/I and Pico-Amp measurement cards. This new test method provides measurement accuracy as high as plusmn10 pA along with up to 9times reduction in test time over conventional parametric testing. The large critical...
An array test structure for highly parallelized measurements of ultra-thin MOS gate oxide failures caused by degradation is presented. The test structure allows for voltage stress tests of several thousand NMOS devices under test (DUTs) in parallel to provide a large and significant statistical base regarding soft as well as hard breakdown and stress induced degradation of transistor parameters. The...
In order to evaluate low contact resistivity precisely, we have developed a new test structure based on cross bridge Kelvin resistor. In this structure, the misalignment margin can be as small as possible. Furthermore, we had successively derived the theoretical expressions to ensure the validity of the newly developed method. This method will enable us to evaluate the silicide to silicon contact...
A method of estimating the subthershold component of MOSFET off-state current (Ioffs) using low-cost, low-resolution fast parallel parametric test is introduced. This method measures the subthreshold slope and uses it to estimate Ioffs. Measurements of individual transistors show a very good agreement between measured Ioffs and Ioffs estimated using our approach. For a simple pad-efficient transistor...
We have proposed and developed a test structure for evaluating electrical characteristics variability of a large number of MOSFETs in very short time using very simple circuit structure. The electrical characteristics such as threshold voltage, subthreshold swings S-factors, random telegraph signal noise, and so on, can be measured in over one million MOSFETs. This new test structure circuit and results...
Test structures used to study the effects of plasma induced damage are complex and time intensive to design; performance problems due to poorly designed components of the structure often confound the desired result. This paper presents a parameterized and hierarchical antenna test structure template that enables the user to characterize the test structure performance and identify safe design guidelines...
A characterization setup for high voltage (HV) LD-MOSFET mismatch and variability determination is presented. The according test chip was successfully realized in 0.35 um HV-CMOS technology. Devices are aligned in rows and columns for gate and drain bias multiplexing and special HV-switches for voltages up to 50 V are controlled by externally generated digital signals. Automatic DC measurements can...
Electrical test structures have been designed to enable the characterisation of corner serif forms of optical proximity correction. These structures measure the resistance of a conducting track with a right angled corner. Varying amounts of OPC have been applied to the outer and inner corners of the feature and the effect on the resistance of the track investigated. A prototype test mask has been...
Theory and experiments are presented of modal decomposition of scattering matrices of multiconductor transmission lines (TLs). In effect, n coupled TLs are decomposed into n independent ones. Its use is demonstrated by applying it to thru-only de-embedding of 4 coupled TLs (synthesized data) and 2 coupled TLs (measurement data from a 0.18 mum-CMOS chip). The proposed de-embedding method could greatly...
This paper presents a comparison between a pure mode and build in balanced characterization of inductor. As predicted by linear electronic theory, the true mode matrix is equal to the build in matrix for small signal analyses. Moreover, we have proposed innovative test structure, de-embedding techniques and parameter extraction methodology which take advantage of mixed mode S-parameters in order to...
In this paper, for the first time, silicon integrated tuner is presented aiming silicon transistor (HBT, MOSFET) millimeter wave (MMW) noise parameters (NFmin, Rn, Gammaopt) extraction through multi-impedance method. This tuner is directly integrated in on-wafer tested transistor test structure. Design, electrical simulation and MMW measurement of the Tuner are described showing capability from 60...
This paper presents an improved model which estimates the geometry required to achieve a desired matching target for rectangular resistors in a semiconductor process. A methodology is explained for estimating the model parameters involved. Measured data is presented which covers an extensive range of geometries on a particular thin film process, and the estimation methodology is followed to derive...
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