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In this work a very simple structure for the implementation of a digital reconfigurable compensator based on specific hardware is presented. Its main advantages are the easy way to change the transfer function by changing the clock frequency of the compensator and the reduction of the required digital resources. This approach can be used in systems implementing capabilities such as autotuning, adaptation...
This paper proposes a novel implementation of an FPGA-Based controller for conducted-noise reduction in dc-dc converters. The switching noise produced by the converter has been reduced by randomly varying the switching frequency of the converter. Traditionally, the implementation of the switching-mode power supply (SMPS) has been accomplished using analog control circuits. However, the field-programmable...
This paper focuses on the non-inverting buck-boost converter supplying an adjustable DC voltage to a WCDMA RF power amplifier (RFPA) in order to improve the system efficiency under different transmitted RF power levels. It is shown that precise output voltage positioning and low output voltage ripple over a wide output voltage range, including buck, boost and buck/boost transition modes, can be accomplished...
Exploiting the capability of an FPGA, a digital current controller of a single-phase inverter for grid interface is designed and implemented. A proportional and resonant (PR) controller realized in a parallel structure in the FPGA is used to reduce the harmonic current to AC grid. The harmonic compensators based on the PR controller are implemented up to the 19th order. The size of the LCL filter...
This paper describes a novel digital control solution for isolated DC-DC converter. Compared with non-isolated DC-DC converters, isolated ones need to realize isolation of control between primary and secondary side. In this paper, the whole digital control system is implemented using two FPGAs. The one on the secondary side includes a compensator (PI regulator), a high resolution digital PWM (DPWM),...
This paper discusses the self-tuning capabilities of an analog current-mode controller for switch-mode DC-DC converters. The proposed tuning techniques are based on the insertion of non-linear blocks in the analog control loop and the generation of a controlled oscillation on the output voltage in order to measure the closed-loop properties like gain margin, phase margin and crossover frequency and...
This paper presents a field programmable gate array (FPGA) implementation of a direct sliding mode current control of a synchronous machine. Due to their robustness to parameters variations and external disturbances, sliding mode controllers are widely used for the control of electrical drives. The main interest of using FPGAs to implement such controllers is the very important reduction of the execution...
A new digital control technique for power factor correction is presented. The main novelty of the method is that there is no current sensor. Instead, the input current is digitally rebuilt, using the estimated input current for the current loop. Apart from that, the ADCs used for the acquisition of the input and output voltages have been designed ad-hoc. Taking advantage of the slow dynamic behavior...
Digital control solutions become more attractive than analog controllers because they allow easy design of more complex control strategies, reconfigurability, high immunity to noise and low power consumption. However, as the control target and power stage of the converter are inherently analog, digital controllers require the addition of Analog-to-Digital (A/D) converters. This data conversion generates...
In this paper, a KY boost converter is presented, which is the KY converter combined with the traditional boost converter. Such a converter has continuous input and output inductor currents, different from the traditional boost converter. And hence this converter is very suitable for low-ripple applications. The detailed illustration of the proposed converter is provided, along with some experimental...
This paper proposes a new FPGA based architecture for digital pulse width modulators which takes advantage of dedicated digital clock manager (DCM) blocks present in modern FPGAs and applies manual placement techniques to match internal delays for high linearity. The proposed hybrid DPWM uses a synchronous counter-based coarse-resolution block and a DCM based fine-resolution block implementing a synchronous...
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