We present a flip-chip integration process in which the vertical alignment is guaranteed by a mechanical contact between pedestals defined in a recess etched into a silicon photonics chip and a laser or semiconductor optical amplifier. By selectively etching up to the active region of the III-V materials, we can make the accuracy of vertical alignment independent on the process control applied to layer thicknesses during silicon photonics or III-V chip fabrication, enabling alignment tolerances below ±10 nm in the vertical (Z-)direction.