The area of SRAM on the chip has increased significantly in recent years (up to 90% in projects of 2014–2015). Thus, the development of the new techniques for accurate estimation of memory block characteristics due to technology variation is required. One of the main problems is the accurate estimation of the minimal voltage difference (MVD), that will reduce the pessimism in the evaluation of performance and yield analysis. In this work we have completed the comparative analysis of existing techniques (based on the worst case method) and the developed method of the accurate estimation of MVD. In the proposed method we use the technique of conditional probabilities, which allows improving the accuracy of estimation. The obtained experimental data shows the possibility of reducing MVD up to 17–22% with the SA number from 256 to 4096.