This paper introduces the differential-mode circulating current (DMCC) and zero-sequence circulating current (ZSCC) reduction method for paralleled inverters with zero common-mode (CM) PWM algorithm. By analyzing the reason of current jump in phase-leg, the method based on the freedom of PWM signal exchange and active voltage vector sequence exchange can be adopted which can keep volt-seconds balance in sector switching period and reduce the peak value of DMCC at the same time. Considering zero-CM PWM algorithm's time segment asymmetric, sub-sector can be divided and PWM signal exchange can also be used to limit the ZSCC. Simulation and experimental results are provided to validate the proposed method and showing that it is beneficial for both DMCC and ZSCC reduction.