In the recent trend of device dimension scaling, parasitic capacitances play pivotal role in determining device performance in ultra low power high speed circuits. In view of this, we have attempted to present a brief study on the analytical modeling of parasitic fringe capacitance of a Tunneling Field Effect transistor with linearly graded binary metal alloy double gate electrode and investigate the impact of device parameters on the capacitance values with an aim to optimize the device parameters in order to bring an improvement in overall device delay performance for future high speed circuits. The obtained analytical results have been compared with SILVACO ATLAS device simulator results for verification of our proposed model.