This paper presents an intrinsically linear wideband polar digital power amplifier (DPA) operating in semi class-E/F2 mode. Without using any type of digital pre-distortion (DPD), the proposed architecture achieves high linearity by accurately controlling its AM–AM and AM–PM characteristic curves through nonlinear sizing, overdrive-voltage control, and multiphase RF clocking without compromising the achievable output power or efficiency. Measurement results of the fabricated prototype in 40-nm bulk CMOS show −46 and −40 dBc adjacent channel power ratio (ACPR) for 20- and 40-MHz orthogonal frequency-division multiplexing (OFDM) signals, respectively. The measured error vector magnitudes (EVM) are −36 dB and −33 dB, respectively. Measured results indicate a $P_{\mathrm{ SAT}}$ , peak drain efficiency (DE), and power-added efficiency (PAE) of 14.6 dBm, 44%, and 26%, respectively, using a 0.5-V supply for the output stage at 2.2 GHz.