Chemical mechanical polishing (CMP) performance influence the reliability of TSV process, because the wafer chip-to-chip vertical interconnections for the next process request the TSV wafer a flat surface without defects after CMP. The influence of ECD process to the CMP defects, further to the via-filling effect, was investigated. Thickness uniformity, top surface morphology and the grain orientation of the copper-filled via prove to be the major factors that lead to the CMP defects: Cu residue, delamination and pits. Optimizing the additives of ECD bath is proved to be a solution to eliminate the CMP defects.