The paper presents an integrated digital communication technique for sending gate signal and gate driver configuration data. As an application example, the developed CMOS gate driver carries the digital data through an optical isolation, in the context of wide bandgap power transistors. The receiver chip integrates all the required functions from the optical receiver to the signal processing circuit (SPC) and the logic control units. The standard AMS HV 0.18 μm CMOS technology is selected for proof of concept and prototyping. A variable frame length serial communication protocol is implemented with an integrated clock to transfer a 4 bit commutation order within 56 ns and an 8 bit configuration data within 84 ns (140 Mbps). Hence, a segmented output stage buffer can be configured by light, thus dynamically changing the gate resistor value through the isolation barrier.