This paper focused on the design of a 2+1- order Switched-current MASH Delta-Sigma ADC with the digital cancellation circuit in TSMC 0.18-µm 1P6M CMOS process. To combat errors in MASH architectures, we have to cancel the errors by utilizing a pertinent digital cancellation circuit; the output of digital code contains the numbers and position of characteristics to the latter part of the digital filter to facilitate the processing. We proposed an algorithm for the logic circuit and employed simplified delay block in digital cancellation circuit to cancel the noise errors from the earlier stage, and to generate a third-order noise shaping output. Our simulation results show that signal-to-noise and distortion ratio (SNDR) is 90.4 dB, and the effective number of bits (ENOB) is 14.73 bits at a sampling rate of 10.24 MHz with an oversampling ratio (OSR) of 256, and the signal bandwidth is 20 kHz. This design draws 12.99 mWfrom the supply voltage of 1.8V and occupies a core area of 0.14 mm2.